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基于BASYS3开发板的vivado开发,封装了一些常见模块_basys3封装

作者：盐析白兔 | 2024-07-25 09:30:09

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basys3封装

Verilog

简介

Verilog 继承了 C 语言的多种操作符和结构，与另一种硬件描述语言 VHDL 相比，语法不是很严格，代码更加简洁，更容易上手。

物质

数据结构

数值

默认为10进制,其他进制可通过以下格式表示

位数+进制(b,o,d,h)+数据 数据可添加下划线增添可读性 4'b1011

字符

reg [0: 14*8-1]       str ;
initial str = "www.baidu.com";

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其他

X表示未知,Z表示高阻

声明

wire表示物理连线 reg表示寄存器

赋值

等号赋值 : 非阻塞<= 阻塞=,即同时赋值和依次赋值

连续赋值: 即将信号与表达式连接,assign对wire变量进行赋值

其他

整数 integer     temp ;
实数 real        temp ;含有小数
时间 time       current_time ; current_time = $time ;
数组 
    integer          flag [7:0] ; //8个整数组成的数组
    reg  [3:0]       counter [3:0] ; //由4个4bit计数器组成的数组
    wire [7:0]       addr_bus [3:0] ; //由4个8bit wire型变量组成的数组
常量 parameter      data_width = 10'd32 ;

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编译指令

以`开始,等同于c语言

`define  DATA_DW     32
`include "header.v"
`timescale  time_unit / time_precision将时间单位与实际时间相关联

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运动

语句

initial always,多个同步执行,内部并行执行 多个语句需要用begin和end进行分离,initial只用于仿真

if (condition1)       true_statement1 ;
else if (condition2)        true_statement2 ;
else if (condition3)        true_statement3 ;
else                      default_statement ;


case(case_expr)
    condition1     :             true_statement1 ;
    condition2     :             true_statement2 ;
    ……
    default        :             default_statement ;
endcase


while (condition) begin
    …
end

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项目步骤

创建项目

  • RTL(不要添加设计源文件)
  • 因为basys3,所以选择xc7a35tcpg236-1

使用vscode

  1. 更换编辑器 tools->setting->text editor->current editor->custom editor->输入C:\Users\killsime\AppData\Local\Programs\Microsoft VS Code\Code.exe -g [file name]:[line number] //前面为vscode的路径,自定义,多个code.exe可以自己试试打开速度,有的比较慢

  2. 安装Verilog-HDL/SystemVerilog/Bluespec SystemVerilog扩展

  3. 添加环境变量,便于设置纠错器,然后就是自动纠错找到安装目录下的 D:\personal\vivado\Vivado\2018.3\bin 添加到path中(用sysdm.cpl打开环境变量编辑器)

  4. 添加纠错器,找到扩展设置中的verilog->linting->linter,修改成xvlog

工程目录下全称

xpr Xilinx Project
ip Intellectual Property
srcs source
sim simulation 
hw Hardware 

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Simulation

以implementation作为界限,分为前仿真和后仿真

前仿真(behavior simulation),在综合编译前验证功能

后仿真(post-implementation),硬件会产生一些延迟

仿真就更像原始的c语言,更方便在逻辑层面调试代码逻辑

RTL analysis

Register Transfer Level

将编程语言对应到元器件得到原理图

RTL->Schematic,会显示理论上原理图

Synthesis

将所有源文件进行综合分析,将原理图映射到FPGA中

Synthesis->Schematic,会显示综合后的原理图

Implementation

实现将综合原理图到硬件端口的对应,所以需要添加约束文件,通过注释的方式添加

或者在rtl的Schematic中ioport进行绑定

BitStream

生成bit流,烧入硬件进行调试

项目文件

设计文件

源文件

module mux21a (
    input wire d0,
    input wire d1,
    input wire sel,
    output wire led
);

    assign led = (~sel & d0) | (sel & d1);
endmodule

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顶层模块

组织其余模块,连接约束文件和源文件的信号

module top_module (
    input wire[2:0] sw,
    output wire[0:0] led //使用数组,以便于后面引脚约束
);

    mux21a M1(
        .d0(sw[0]),
        .d1(sw[1]),
        .sel(sw[2]),
        .led(led[0])
    );

endmodule

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仿真文件

简介

仿真可以得到模块运行时的波形图

本质也是verilog代码,只是没有输入的模块,按时序给变量赋值

一般执行前仿真,看逻辑有没有错误,在有性能问题时再执行后仿真

注意点

  1. 输出一定要用wire类型接收
  2. 一般习惯把模块命名为testbench(测试台),或者在多个仿真时ModuleName_tb
  3. 仿真前,先将仿真文件set as top
  4. 执行仿真后,打开新生成的untitled文件,zoom fit以便于观察波形图

系统任务

就是调试语句,方便我们再Tcl console中查看我们想要的信息
除了仿真后的波形图查看模块中变量的值,我们还可以添加调试语句便于查看和控制过程中的值

display

跟c语言的printf类似,会自动换行

display会按数据最大宽度自动调整输出格式

常用占位符;
数字类 : %b %o %d %h 2/8/10/16进制输出  %e 科学计数法
字符类 : %c ascii字符 %s 字符串
特殊类 : %t时间,与$time搭配使用

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字符会自动拼接

$display("hello ","world-",$time);
$display("32位随机整数 : %d",  $random);

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类似的有write,不会自动换行

monitor

用于监视变量的值,当有参数变化时输出,可以控制开关

integer i=0;
initial forever #5 i=i+1;
initial $monitor("time=",$time," i=%d",i);
initial  #20 $monitoroff;

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类似的有strobe,在结束时输出

finish

结束,可以跟参数,得到不同的信息,默认为0

0 : 无信息
1 : 仿真时间和位置
2 : 仿真时间和位置,以及memory和cpu时间统计

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类似的有stop,功能是暂停

timescale

timescale 1ns/1ps 时间单位/时间精度

时间单位,即#10这种延迟的单位

时间精度,即生成波形图的横坐标

约束文件

使用时将所需引脚取消注释就行

## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project

## Clock signal
#set_property PACKAGE_PIN W5 [get_ports clk]
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

## Switches
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]


## LEDs
#set_property PACKAGE_PIN U16 [get_ports {led[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
#set_property PACKAGE_PIN E19 [get_ports {led[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
#set_property PACKAGE_PIN U19 [get_ports {led[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
#set_property PACKAGE_PIN V19 [get_ports {led[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]


##7 segment display
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

#set_property PACKAGE_PIN V7 [get_ports dp]
#set_property IOSTANDARD LVCMOS33 [get_ports dp]

#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]


##Buttons
#set_property PACKAGE_PIN U18 [get_ports btnC]
#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
#set_property PACKAGE_PIN T18 [get_ports btnU]
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
#set_property PACKAGE_PIN T17 [get_ports btnR]
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
#set_property PACKAGE_PIN U17 [get_ports btnD]
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]



##Pmod Header JA
##Sch name = JA1
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
##Sch name = JA2
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
##Sch name = JA3
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
##Sch name = JA4
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
##Sch name = JA7
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
##Sch name = JA8
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
##Sch name = JA9
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
##Sch name = JA10
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]



##Pmod Header JB
##Sch name = JB1
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
##Sch name = JB2
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
##Sch name = JB3
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
##Sch name = JB4
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
##Sch name = JB7
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
##Sch name = JB8
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
##Sch name = JB9
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
##Sch name = JB10
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]



##Pmod Header JC
##Sch name = JC1
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
##Sch name = JC2
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]


##Pmod Header JXADC
##Sch name = XA1_P
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
##Sch name = XA2_P
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
##Sch name = XA3_P
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
##Sch name = XA4_P
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
##Sch name = XA1_N
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
##Sch name = XA2_N
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]



##VGA Connector
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
#set_property PACKAGE_PIN P19 [get_ports Hsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
#set_property PACKAGE_PIN R19 [get_ports Vsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]


##USB-RS232 Interface
#set_property PACKAGE_PIN B18 [get_ports RsRx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
#set_property PACKAGE_PIN A18 [get_ports RsTx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]


##USB HID (PS/2)
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
#set_property PULLUP true [get_ports PS2Clk]
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
#set_property PULLUP true [get_ports PS2Data]


##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]

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常用模块

使用模块注意事项

输出需要用wire类型接受

led

LED_1

显示一个数字

`timescale 1ns / 1ps
module LED_1
    (
        input wire clk,   
        input  [13:0] num,
        output wire [3:0] an1,    
        output wire [6:0] seg    
    );
    
    reg [3:0]i_num_1;
    reg [3:0]i_num_2;
    reg [3:0]i_num_3;
    reg [3:0]i_num_4;
    
    always@(*)
    begin
    i_num_1 = num%10000/1000;
    i_num_2 = num%1000/100;
    i_num_3 = num%100/10;
    i_num_4 = num%10/1;
    end
    

    reg [3:0] an;    
    reg [6:0] o_led_num;  
    reg [17:0] regN;    
    
    always @(posedge clk)
        regN <= regN+1;    
        
    reg[3:0] i_num;   
    always @(*)  
    begin
        case (regN[17:16])
        2'b00:begin
                an=4'b0111;
                i_num=i_num_1;
                end
        2'b01:begin
                an=4'b1011;
                i_num=i_num_2;
                end      
        2'b10:begin
                an=4'b1101;
                i_num=i_num_3;
                end  
        2'b11:begin 
                an=4'b1110;
                i_num=i_num_4;
                end
       endcase
    end
                   
    
    always @ *    
        begin
            case(i_num)
            4'h0:o_led_num = 7'b100_0000;
            4'h1:o_led_num = 7'b111_1001;
            4'h2:o_led_num = 7'b010_0100;
            4'h3:o_led_num = 7'b011_0000;
            4'h4:o_led_num = 7'b001_1001;
            4'h5:o_led_num = 7'b001_0010;
            4'h6:o_led_num = 7'b000_0010;
            4'h7:o_led_num = 7'b111_1000;
            4'h8:o_led_num = 7'b000_0000;
            4'h9:o_led_num = 7'b001_0000;
            default:   
                 o_led_num = 7'b111_1111;
            endcase
         end  
         
    assign seg = o_led_num;
    assign an1 = an;
    
endmodule



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LED_4

分别显示四位

`timescale 1ns / 1ps
//输入一个数字
module LED_1
    (
        input wire clk,   
        input  [13:0] num,
        output wire [3:0] an1,    
        output wire [6:0] seg    
    );
    
    reg [3:0]i_num_1;
    reg [3:0]i_num_2;
    reg [3:0]i_num_3;
    reg [3:0]i_num_4;
    
    always@(*)
    begin
    i_num_1 = num%10000/1000;
    i_num_2 = num%1000/100;
    i_num_3 = num%100/10;
    i_num_4 = num%10/1;
    end
    

    reg [3:0] an;    
    reg [6:0] o_led_num;  
    reg [17:0] regN;    
    
    always @(posedge clk)
        regN <= regN+1;    
        
    reg[3:0] i_num;   
    always @(*)  
    begin
        case (regN[17:16])
        2'b00:begin
                an=4'b0111;
                i_num=i_num_1;
                end
        2'b01:begin
                an=4'b1011;
                i_num=i_num_2;
                end      
        2'b10:begin
                an=4'b1101;
                i_num=i_num_3;
                end  
        2'b11:begin 
                an=4'b1110;
                i_num=i_num_4;
                end
       endcase
    end
                   
    
    always @ *    
        begin
            case(i_num)
            4'h0:o_led_num = 7'b100_0000;
            4'h1:o_led_num = 7'b111_1001;
            4'h2:o_led_num = 7'b010_0100;
            4'h3:o_led_num = 7'b011_0000;
            4'h4:o_led_num = 7'b001_1001;
            4'h5:o_led_num = 7'b001_0010;
            4'h6:o_led_num = 7'b000_0010;
            4'h7:o_led_num = 7'b111_1000;
            4'h8:o_led_num = 7'b000_0000;
            4'h9:o_led_num = 7'b001_0000;
            default:   
                 o_led_num = 7'b111_1111;
            endcase
         end  
         
    assign seg = o_led_num;
    assign an1 = an;
    
endmodule

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clk_div

`timescale 1ns / 1ps


module clk_div #(parameter div=1)(//得到1/div秒的时钟信号
    input clk,
    output reg clk_out
    );

parameter N = 99999999; 
reg [31:0] count;

always @(posedge clk) 
begin
    if (count < N/div) 
    begin
        count   <= count + 1;
        clk_out <= 0;
    end
    else 
    begin
        count   <= 0;
        clk_out <= 1;
    end
end

endmodule

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clock

输出过了多少秒

`timescale 1ns / 1ps

module clock(
    input clk,
    output reg [15:0] sec
    );
    reg [31:0] count;  
    always @(posedge clk) begin
    count <= count + 1;
    if (count == 100000000) begin
        count <= 32'h00000000;
        sec <= sec + 1;
        end
    end
endmodule

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anti_shake

`timescale 1ns / 1ps

module anti_shake(
    input  clk,
    input  i_btn,
    output reg o_btn
    );

wire clk_200ms;
clk_div #(5) u11(clk,clk_200ms);

always @(posedge clk_200ms)
    o_btn=i_btn;
endmodule

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批量时

xdc
set_property PACKAGE_PIN T18 [get_ports {btn[0]}]
set_property PACKAGE_PIN W19 [get_ports {btn[1]}]
set_property PACKAGE_PIN U18 [get_ports {btn[2]}]
set_property PACKAGE_PIN T17 [get_ports {btn[3]}]
set_property PACKAGE_PIN U17 [get_ports {btn[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[0]}]

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use
reg [31:0] cnt;
wire btn;
anti_shake u1(clk,btnC,btn);
always @(posedge clk) if(btn)cnt<=cnt+1;   //replace btnC by btn,to compare the difference
LED_1 led1(clk,cnt/1000000,an,seg);
assign led = btn;

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set,stop

对模块的使能信号和暂停可以这么写,这两个信号通过拨码开关输入

always@(posedge clk,negedge set,negedge stop)begin
    if(!set)begin 
        if(!stop)   state<=s0;
        else        state<=state;
    end
    else           //正常该执行的代码
        state <=state_next;
end

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IP核

代码复用

封装

如与门

module andgate
    #(parameter WIDTH = 8)
    (
    input[(WIDTH-1):0] a,
    input[(WIDTH-1):0] b,
    output[(WIDTH-1):0] c
    );
    
    assign c = a&b;
endmodule

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在仿真验证后开始封装

  1. project setting->IP->packeger->勾选所有after packaging
  2. Tools->Create and Package IP 一路next(记一下ip核的位置)
  3. Compatibility ->Add Family Explicitly ->选中除 artix7 之外的所有芯片家族（因为 artix7 系列已经有了）
  4. Package IP

调用

  1. project setting->IP->repository->添加选择封装的IP核解压后的目录
  2. create block design->IP Catalog->双击所需IP进行添加
  3. 添加输入输出端口: 点击空白处->port
  4. 在design文件右键,创建 HDL wapper ,将IP核进行包装 ,默认勾选让vivado接管,如果以及生成需要删掉重新生成
  5. 依旧design右键,generate output products->global

使用时,可以ctrl+t一键添加端口

下载

xupgit/Basys3: XUP Basys3 Boards’ LIBs and Projects (github.com)

解压后再将basys.zip解压后放到D:\personal\vivado\Vivado\2018.3\data\boards\board_parts\artix7

然后调用时添加压缩包解压的文件夹

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