HDLBits答案(14)_Verilog有限状态机(1)_verilog 状态机考试题

Verilog有限状态机(1)

HDLBits链接

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前言

今天来到了重要的部分：状态机。对该部分内容，可能不会一次更新一个小节；一方面是题目难度，另一方面是代码量过大；所以该节会分批更新，大家见谅。

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题库

题目描述1：

实现下图所示的摩尔状态机，复位为异步复位。

Solution1：

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        case(state)
            A:begin
                if(in == 1'b1)begin
                    next_state = A;
                end
                else begin
                    next_state = B;
                end
            end
            B:begin
                if(in == 1'b1)begin
                    next_state = B;
                end
                else begin
                    next_state = A;
                end
            end
        endcase
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset)begin
            state <= B;
        end
        else begin
            state <= next_state;
        end
    end

    // Output logic
    assign out = (state == B);

endmodule
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题目描述2：

实现下图所示的摩尔状态机，复位为同步复位。

Solution2：

module top_module(
    input clk,
    input reset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        case(state)
            A:begin
                if(in == 1'b1)begin
                    next_state = A;
                end
                else begin
                    next_state = B;
                end
            end
            B:begin
                if(in == 1'b1)begin
                    next_state = B;
                end
                else begin
                    next_state = A;
                end
            end
        endcase
    end

    always @(posedge clk) begin    // This is a sequential always block
        if(reset)begin
            state <= B;
        end
        else begin
            state <= next_state;
        end
    end

    // Output logic
    assign out = (state == B);

endmodule
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题目描述3：

2个输入1个输出，异步复位状态机，如下图所示。

Solution3：

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        case(state)
            OFF:begin
                if(j == 0)begin
                    next_state = OFF;
                end
                else begin
                    next_state = ON;
                end
            end
            ON:begin
                if(k == 0)begin
                    next_state = ON;
                end
                else begin
                    next_state = OFF;
                end
            end
        endcase
    end

    always @(posedge clk, posedge areset) begin
        if(areset)begin
            state <= OFF;
        end
        else begin
        	state <= next_state;
        end
    end

    // Output logic
    assign out = (state == ON);

endmodule
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题目描述4：

2个输入1个输出，同步复位状态机，如下图所示。

Solution4：

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;

    always @(*) begin
        case(state)
            OFF:begin
                if(j == 0)begin
                    next_state = OFF;
                end
                else begin
                	next_state = ON;
                end
            end
            ON:begin
                if(k == 0)begin
                    next_state = ON;
                end
                else begin
                	next_state = OFF;
                end
            end
        endcase
    end

    always @(posedge clk) begin
        if(reset)begin
            state <= OFF;
        end
        else begin
            state <= next_state;
        end
    end

    // Output logic
    assign out = (state == ON);

endmodule
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题目描述5：

实现下面的摩尔状态机，下表是状态转移图，1输入1输出4状态。

Solution5：

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    always @(*)begin
        case(state)
            A:begin
                if(in == 0)begin
                	next_state = A;
                end
                else begin
                	next_state = B;
                end
            end
            B:begin
                if(in == 0)begin
                	next_state = C;
                end
                else begin
                	next_state = B;
                end
            end
            C:begin
                if(in == 0)begin
                	next_state = A;
                end
                else begin
                	next_state = D;
                end
            end
            D:begin
                if(in == 0)begin
                	next_state = C;
                end
                else begin
                	next_state = B;
                end
            end
        endcase
    end

    assign out = (state == D);

endmodule
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小结

今天先更新这五道题，主要是熟悉三段式状态机的编写。

若是代码有误请大家提醒我，我一定尽快改正。