Circuits--Sequential--Finite4

1. Simple  FSM3 asy

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
 
    parameter A=2'd0;
    parameter B=2'd1;
    parameter C=2'd2;
    parameter D=2'd3;
    
    reg[1:0] state;
    reg[1:0] next_state;
    
    // State transition logic
    always@(*)
        begin
            case(state)
                A:
                    begin
                        if(in==0) next_state = A;
                        else next_state = B;
                    end
                B:
                    begin
                        if(in==0) next_state = C;
                        else next_state = B;
                    end
                C:
                    begin
                        if(in==0) next_state = A;
                        else next_state = D;
                    end
                D:
                    begin
                        if(in==0) next_state = C;
                        else next_state = B;
                    end
            endcase
        end
 
    // State flip-flops with asynchronous reset
    always@(posedge clk or posedge areset)
        begin
            if(areset)
                state = A;
            else
                state = next_state;
        end
 
    // Output logic
    assign out = (state == D);
 
endmodule

2. Simple FSM3 sy

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
 
    parameter A=2'd0;
    parameter B=2'd1;
    parameter C=2'd2;
    parameter D=2'd3;
    
    reg[1:0] state;
    reg[1:0] next_state;
    
    // State transition logic
    always@(*)
        begin
            case(state)
                A:
                    begin
                        if(in==0) next_state = A;
                        else next_state = B;
                    end
                B:
                    begin
                        if(in==0) next_state = C;
                        else next_state = B;
                    end
                C:
                    begin
                        if(in==0) next_state = A;
                        else next_state = D;
                    end
                D:
                    begin
                        if(in==0) next_state = C;
                        else next_state = B;
                    end
            endcase
        end
 
    // State flip-flops with asynchronous reset
    always@(posedge clk )
        begin
            if(reset)
                state = A;
            else
                state = next_state;
        end
 
    // Output logic
    assign out = (state == D);
 
endmodule