vivado下载bit流时出现引脚约束错误_vivado has both clkardclk and clkbwrclk

项目场景：

从完整项目中删去一些模块时留了一些空置引脚

问题描述

同时报了以下错误

[DRC NSTD-1] Unspecified I/O Standard: 16 out of 263 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GT_SERIAL_TX_0_txn[0:3], GT_SERIAL_TX_0_txp[0:3], GT_SERIAL_TX_1_txn[0:3], and GT_SERIAL_TX_1_txp[0:3].
 

[DRC UCIO-1] Unconstrained Logical Port: 16 out of 263 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: GT_SERIAL_TX_0_txn[0:3], GT_SERIAL_TX_0_txp[0:3], GT_SERIAL_TX_1_txn[0:3], and GT_SERIAL_TX_1_txp[0:3].
[DRC REQP-1947] RAMB36E2_CLKs_TIEOFF_invalid: The RAMB36E2 cell     xxxx/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has both CLKARDCLK and CLKBWRCLK connected to VCC and/or GROUND. The BRAM will not operate correctly unless at least one clock is connected to an ACTIVE signal.
[DRC REQP-1947] RAMB36E2_CLKs_TIEOFF_invalid: The RAMB36E2 cell xxxx/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has both CLKARDCLK and CLKBWRCLK connected to VCC and/or GROUND. The BRAM will not operate correctly unless at least one clock is connected to an ACTIVE signal.



[DRC REQP-1947] RAMB36E2_CLKs_TIEOFF_invalid: The RAMB36E2 cell xxxx/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has both CLKARDCLK and CLKBWRCLK connected to VCC and/or GROUND. The BRAM will not operate correctly unless at least one clock is connected to an ACTIVE signal.[DRC REQP-1947] RAMB36E2_CLKs_TIEOFF_invalid: The RAMB36E2 cell xxxx/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram has both CLKARDCLK and CLKBWRCLK connected to VCC and/or GROUND. The BRAM will not operate correctly unless at least one clock is connected to an ACTIVE signal.

原因分析：

删除后引脚悬空，删完后没有处理到位

解决方案：

第一块为没有分配引脚，到引脚分配分配一下I/O口就好了，如果有点号就根据点号来，如果只是上板，就随意分配一下。

GTX和GTH的IP的引脚如果没有删干净会引起错误，如果没有对存在的引脚进行约束也会报错，约束的类型如果为default（LVDSCMOS）要把default去掉，否则也会报错。