【入门教程一】基于DE2-115的My First FPGA 工程

module my_first_fpga(
        input  wire clk,        // 50MHz input clock
        output wire LED         // LED ouput
);
 
// create a binary counter
reg [31:0] cnt;                 // 32-bit counter
 
initial begin
 
cnt <= 32'h00000000;            // start at zero
end
always @(posedge clk) begin
cnt <= cnt + 1;                 // count up
end
//assign LED to 25th bit of the counter to blink the LED at a few Hz
assign LED = cnt[24];
endmodule

# inform quartus that the clk port brings a 50MHz clock into our design so
# that timing closure on our design can be analyzed
 
create_clock -name clk -period "50MHz" [get_ports clk]
 
# inform quartus that the LED output port has no critical timing requirements
# its a single output port driving an LED, there are no timing relationships
# that are critical for this
 
set_false_path -from * -to [get_ports LED]