学习笔记之FPGA的IP核及其应用_fpgaip核

2.2 PLL核的调用

        实验代码

`timescale 1ns / 1ps
 
module pll_test(
	input   clk,
	input   rst_n,
	output  clkout1,        //pll clock output
	output  clkout2,        //pll clock output
	output  clkout3,        //pll clock output
	output  clkout4         //pll clock output
	);
 
wire locked;
 
pll pll_inst
(
	// Clock in ports
	.inclk0(clk),           // IN 50Mhz
	// Clock out ports
	.c0(clkout1),           // OUT 25Mhz
	.c1(clkout2),           // OUT 50Mhz
	.c2(clkout3),           // OUT 75Mhz
	.c3(clkout4),           // OUT 100Mhz
	// Status and control signals
	.areset(~rst_n),        // IN
	.locked(locked)         //The signal of PLL normal operation
	);                      // OUT
 
endmodule

        测试文件           

`timescale 1ns / 1ps        //仿真单位/仿真精度
 
module pll_test_tb();
 
//parameter define
parameter  CLK_PERIOD = 20; //时钟周期 20ns
 
//reg define
reg     sys_clk;
reg     sys_rst_n;
 
//wire define
wire    clk_100m;      
wire    clk_100m_180deg;
wire    clk_50m;     
wire    clk_25m;        
 
//信号初始化
initial begin
    sys_clk = 1'b0;
    sys_rst_n = 1'b0;
    #200
    sys_rst_n = 1'b1;
end
//产生时钟
always #(CLK_PERIOD/2) sys_clk = ~sys_clk;
pll_test u_pll_test(
	.clk					(sys_clk   ),
	.rst_n				(sys_rst_n ),
	.clkout1				(clk_25m   ),        //pll clock output
	.clkout2				(clk_50m   ),        //pll clock output
	.clkout3				(clk_75m   ),        //pll clock output
	.clkout4				(clk_100m  )         //pll clock output
	);
endmodule

module ram_1p_top( 
    input               sys_clk        ,  //系统时钟
    input               sys_rst_n         //系统复位，低电平有效
 
    );
 
//wire define
wire             ram_wr_en   ;  //ram写使能  
wire             ram_rd_en   ;  //ram读使能  
wire    [4:0]    ram_addr    ;  //ram读写地址 
wire    [7:0]    ram_wr_data ;  //ram写数据  
 
wire    [7:0]    ram_rd_data ;  //ram读数据  
 
//*****************************************************
//**                    main code
//*****************************************************
 
//ram读写模块
ram_rw  u_ram_rw(
    .clk            (sys_clk),
    .rst_n          (sys_rst_n),
 
    .ram_wr_en      (ram_wr_en  ),
    .ram_rd_en      (ram_rd_en  ),
    .ram_addr       (ram_addr   ),
    .ram_wr_data    (ram_wr_data),
 
    .ram_rd_data    (ram_rd_data)
    );
 
//ram ip核
ram_1port  u_ram_1port(
    .address      (ram_addr),
    .clock        (sys_clk),
    .data         (ram_wr_data),
    .rden         (ram_rd_en),
    .wren         (ram_wr_en),
    .q            (ram_rd_data)
    );
    
endmodule    

module ram_rw( 
    input               clk        ,  //时钟信号
    input               rst_n      ,  //复位信号，低电平有效
    
    output              ram_wr_en  ,  //ram写使能
    output              ram_rd_en  ,  //ram读使能
    output  reg  [4:0]  ram_addr   ,  //ram读写地址
    output  reg  [7:0]  ram_wr_data,  //ram写数据
    
    input        [7:0]  ram_rd_data   //ram读数据        
 );
 
//reg define
reg    [5:0]  rw_cnt ;                //读写控制计数器
 
//*****************************************************
//**                    main code
//*****************************************************
 
//rw_cnt计数范围在0~31,ram_wr_en为高电平;32~63时,ram_wr_en为低电平
assign  ram_wr_en = ((rw_cnt >= 6'd0) && (rw_cnt <= 6'd31) && rst_n)  ?  1'b1  :  1'b0;
//rw_cnt计数范围在32~63,ram_rd_en为高电平;0~31时,ram_rd_en为低电平
assign  ram_rd_en = ((rw_cnt >= 6'd32) && (rw_cnt <= 6'd63))  ?  1'b1  :  1'b0;
 
//读写控制计数器,计数器范围0~63
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)
        rw_cnt <= 6'd0;    
    else if(rw_cnt == 6'd63)
        rw_cnt <= 6'd0;
    else
        rw_cnt <= rw_cnt + 6'd1;    
end    
//读写控制器计数范围：0~31 产生ram写使能信号和写数据信号
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)
        ram_wr_data <= 8'd0;  
    else if(rw_cnt >= 6'd0 && rw_cnt <= 6'd31)
        ram_wr_data <= ram_wr_data + 8'd1;
    else
        ram_wr_data <= 8'd0;         
end    
//读写地址信号 范围:0~31
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)
        ram_addr <= 5'd0;
    else if(ram_addr == 5'd31)
        ram_addr <= 5'd0;
    else
        ram_addr <= ram_addr + 1'b1; 
end
 
endmodule

//这部分代码在设置好IP核后自动生成
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_1port (
	address,
	clock,
	data,
	rden,
	wren,
	q);
 
	input	[4:0]  address;
	input	  clock;
	input	[7:0]  data;
	input	  rden;
	input	  wren;
	output	[7:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
	tri1	  clock;
	tri1	  rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
 
	wire [7:0] sub_wire0;
	wire [7:0] q = sub_wire0[7:0];
 
	altsyncram	altsyncram_component (
				.address_a (address),
				.clock0 (clock),
				.data_a (data),
				.rden_a (rden),
				.wren_a (wren),
				.q_a (sub_wire0),
				.aclr0 (1'b0),
				.aclr1 (1'b0),
				.address_b (1'b1),
				.addressstall_a (1'b0),
				.addressstall_b (1'b0),
				.byteena_a (1'b1),
				.byteena_b (1'b1),
				.clock1 (1'b1),
				.clocken0 (1'b1),
				.clocken1 (1'b1),
				.clocken2 (1'b1),
				.clocken3 (1'b1),
				.data_b (1'b1),
				.eccstatus (),
				.q_b (),
				.rden_b (1'b1),
				.wren_b (1'b0));
	defparam
		altsyncram_component.clock_enable_input_a = "BYPASS",
		altsyncram_component.clock_enable_output_a = "BYPASS",
		altsyncram_component.intended_device_family = "Cyclone IV E",
		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
		altsyncram_component.lpm_type = "altsyncram",
		altsyncram_component.numwords_a = 32,
		altsyncram_component.operation_mode = "SINGLE_PORT",
		altsyncram_component.outdata_aclr_a = "NONE",
		altsyncram_component.outdata_reg_a = "UNREGISTERED",
		altsyncram_component.power_up_uninitialized = "FALSE",
		altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
		altsyncram_component.widthad_a = 5,
		altsyncram_component.width_a = 8,
		altsyncram_component.width_byteena_a = 1;
endmodule

`timescale  1ns/1ns   //仿真的单位/仿真的精度
 
module ip_1port_ram_tb();
 
 
reg          sys_clk;
reg          sys_rst_n;   
 
 
initial begin
    sys_clk = 1'b0;
    sys_rst_n = 1'b0;
    #50
    sys_rst_n = 1'b1;
end
always #20 sys_clk = ~sys_clk; 
ram_1p_top u_ram_1p_top(
    .sys_clk            (sys_clk  ), 
    .sys_rst_n          (sys_rst_n)
    );
    
endmodule

module fifo_rd(
	input					clk,
	input					rst_n,
	
	//fifo
	input					rd_full,
	input					rd_empty,
	output				rd_re,
	input			[7:0]	rd_data
	
);
 
reg	rd_flag;
assign	rd_re	=	(~rd_empty)	&	rd_flag;//防止数据溢出
	
always@(posedge clk or	negedge	rst_n)
	begin
		if(!rst_n)
			rd_flag	<=	1'b0;
		else if(rd_full)
			rd_flag	<=	1'b1;
		else if(rd_empty)
			rd_flag	<=	1'b0;
	end
	
endmodule

module fifo_rd(
	input					clk,
	input					rst_n,
	
	//fifo
	input					rd_full,
	input					rd_empty,
	output				rd_re,
	input			[7:0]	rd_data
	
);
 
reg	rd_flag;
assign	rd_re	=	(~rd_empty)	&	rd_flag;//防止数据溢出
	
always@(posedge clk or	negedge	rst_n)
	begin
		if(!rst_n)
			rd_flag	<=	1'b0;
		else if(rd_full)
			rd_flag	<=	1'b1;
		else if(rd_empty)
			rd_flag	<=	1'b0;
	end
	
endmodule

module fifo_test(
    input    sys_clk    ,      //时钟信号
    input    sys_rst_n         //复位信号
    );
 
//wire define
wire                clk_50m ;  //50Mhz时钟  
wire                clk_25m ;  //25Mhz时钟   
wire                locked  ;  //时钟稳定信号
 
wire                rst_n   ;  //复位信号   
 
wire     [7:0]      rd_usedw;  //读侧FIFO中的数据量
wire     [7:0]      wr_usedw;  //写侧FIFO中的数据量
 
wire                wr_full ;  //写侧满信号
wire                wr_empty;  //写侧空信号
wire                wr_req  ;  //写请求信号
wire     [7:0]      wr_data ;  //写入FIFO的数据
 
wire                rd_full ;  //读侧满信号
wire                rd_empty;  //读侧空信号
wire                rd_req  ;  //读请求信号
wire     [7:0]      rd_data ;  //读出FIFO的数据
 
//*****************************************************
//**                    main code
//*****************************************************
 
//待时钟输出稳定后,再拉高rst_n信号
assign rst_n = sys_rst_n & locked;
 
//例化锁相环模块    
pll	u_pll_clk (
    .areset (~sys_rst_n ),
    .inclk0 (sys_clk ),
    .c0     (clk_25m ),
    .c1     (clk_50m ),
    .locked (locked )
    );    
 
//例化FIFO写模块
fifo_wr u_fifo_wr(
    .clk        (clk_50m),  
    .rst_n      (rst_n),
 
    .wr_full    (wr_full ),
    .wr_empty   (wr_empty),
    .wr_re     (wr_re  ),
    .wr_data    (wr_data )
    );
 
//例化异步FIFO模块    
fifo_ip	u_async_fifo (
    .aclr       (~rst_n ),
    .data       (wr_data ),
    .rdclk      (clk_25m ),
    .rdreq      (rd_re ),
    .wrclk      (clk_50m ),
    .wrreq      (wr_re ),
    .q          (rd_data ),
    .rdempty    (rd_empty ),
    .rdfull     (rd_full ),
    .rdusedw    (rd_usedw ),
    .wrempty    (wr_empty ),
    .wrfull     (wr_full ),
    .wrusedw    (wr_usedw )
    );
 
//例化FIFO读模块
fifo_rd u_fifo_rd(
    .clk         (clk_25m),
    .rst_n       (rst_n),
 
    .rd_full     (rd_full ),
    .rd_empty    (rd_empty),
    .rd_re      (rd_re  ),
    .rd_data     (rd_data )
    );
  
endmodule   

测试文件

`timescale  1ns/1ns   //仿真的单位/仿真的精度
 
module fifo_tb();
 
 
reg          sys_clk;
reg          sys_rst_n;   
 
initial begin
    sys_clk = 1'b0;
    sys_rst_n = 1'b0;
    #100
    sys_rst_n = 1'b1;
end
always #20 sys_clk = ~sys_clk; 
fifo_tset u_ip_fifo(
    .sys_clk            (sys_clk  ), 
    .sys_rst_n          (sys_rst_n)
    );
    
endmodule