FIFO设计

1 同步FIFO

下图展示了一个同步fifo的通用架构。

其中双端口ROM（DPRAM）作为同步FIFO的存储器使用，由于读写控制时钟均为同一个clk故称为同步fifo，另外fifo_full和fifo_empty为fifo空满状态标志位，wr_en和rd_en控制fifo的读写使能，内部寄存器wr_ptr与rd_ptr受上述三组信号控制，并且作为存储器的地址，控制DPRAM的读写。
同步FIFO代码：

module FIFO4_4(
output reg fifo_full = 1'b1,
output reg fifo_empty = 1'b0,
output reg [3 : 0] fifo_dout,
input fifo_clk,
input fifo_rstn,
input fifo_rd_en,
input fifo_wr_en,
input [3 : 0] fifo_din
);

parameter width = 4, depth = 4;
reg [width - 1 : 0] fifo_mem [depth - 1 : 0];
reg [3 : 0] rdp, wrp;
//counter
always @(posedge fifo_clk) begin
    if( !fifo_rstn ) wrp <= 1'b0;
    else if( (!fifo_full) || (fifo_wr_en) ) wrp <= wrp;
    else if( wrp < depth - 1 ) wrp <= wrp + 1'b1;
    else wrp <= 1'b0;
end
always @(posedge fifo_clk) begin
    if( !fifo_rstn ) rdp <= 1'b0;
    else if( (!fifo_empty) || (fifo_rd_en) ) rdp <= rdp;
    else if( rdp < depth - 1 ) rdp <= rdp + 1'b1;
    else rdp <= 1'b0;
end
//detect full or empty
always @(posedge fifo_clk) begin
    if( !fifo_rstn ) fifo_full <= 1'b1;
    else if( !fifo_rd_en ) fifo_full <= 1'b1;
    else if( (wrp - rdp) == (depth - 1) || wrp + 1'b1 == rdp ) fifo_full <= 1'b0;
    else if( wrp == rdp ) fifo_full <= fifo_full;
    else fifo_full <= 1'b1;
end
always @(posedge fifo_clk) begin
    if( !fifo_rstn ) fifo_empty <= 1'b0;
    else if( !fifo_wr_en ) fifo_empty <= 1'b1;
    else if( (rdp - wrp) == (depth - 1) || rdp + 1'b1 == wrp ) fifo_empty <= 1'b0;
    else if( wrp == rdp ) fifo_empty <= fifo_empty;
    else fifo_empty <= 1'b1;
end
//write or read data
always @(posedge fifo_clk) begin
    if( !fifo_rstn ) begin
        fifo_mem[0] <= 4'b0;
        fifo_mem[1] <= 4'b0;
        fifo_mem[2] <= 4'b0;
        fifo_mem[3] <= 4'b0;
    end
    else if( (!fifo_wr_en) && (fifo_full) ) fifo_mem[wrp] <= fifo_din;
    else fifo_mem[wrp] <= fifo_mem[wrp];
end
always @(posedge fifo_clk) begin
    if( !fifo_rstn ) fifo_dout <= 4'b0;
    else if( (!fifo_rd_en) && (fifo_empty) ) fifo_dout <= fifo_mem[rdp];
    else fifo_dout <= 4'b0;
end
endmodule
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仿真结果（布局后时序仿真）：

FIFO IP coreÿ