Xilinx官方文档系列（二）Vivado Design Suite 用户指南：设计流程概述_xilinx管饭文档

一、Vivado System-Level Design Flows（vivado系统级设计流程）

1、Navigating Content by Design Process

2、Industry Standards-Based Design

3、Design Flows（设计流程）

①、传统设计流程：

4、RTL-to-Bitstream Design Flow（RTL到比特流的设计流程）

①、RTL Design（RTL设计）
You can specify RTL source files to create a project and use these sources for RTL code development, analysis, synthesis and implementation. AMD supplies a library of recommended RTL and constraint templates to ensure RTL and XDC are formed optimally for use with the Vivado Design Suite. Vivado synthesis and implementation support multiple source file types,
including Verilog, VHDL, SystemVerilog, and XDC. For information on creating and working with an RTL project, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
您可以指定 RTL 源文件来创建项目，并将这些源用于 RTL 代码开发、分析、综合和实现。AMD 提供推荐的 RTL 和约束模板库，以确保 RTL 和 XDC 以最佳方式与 Vivado 设计套件配合使用。Vivado 综合和实施支持多种源文件类型，包括 Verilog、VHDL、SystemVerilog 和 XDC。有关创建和使用 RTL 项目的信息，请参见 Vivado 设计套件用户指南：系统级设计入门级 （UG895） 中的此链接。

②、IP Design and System-Level Design Integration（IP设计和系统级设计集成）
The Vivado Design Suite provides an environment to configure, implement, verify, and integrate IP as a standalone module or within the context of the system-level design. IP can include logic,embedded processors, digital signal processing (DSP) modules, or C-based DSP algorithm designs. Custom IP is packaged following IP-XACT protocol and then made available through the
Vivado IP catalog. The IP catalog provides quick access to the IP for configuration, instantiation,and validation of IP. AMD IP utilizes the AXI4 interconnect standard to enable faster system-level integration. Existing IP can be used in the design either in RTL or netlist format. For more information, see the Vivado Design Suite User Guide: Designing with IP (UG896).
Vivado 设计套件提供了一个环境，用于将 IP 作为独立模块或在系统级设计环境中进行配置、实现、验证和集成。IP 可以包括逻辑、嵌入式处理器、数字信号处理 （DSP） 模块或基于 C 的 DSP 算法设计。
定制 IP 按照 IP-XACT 协议进行打包，然后通过 Vivado IP 目录提供。
IP 目录提供对 IP 的快速访问，以便对 IP 进行配置、实例化和验证。
AMD IP 利用 AXI4 互连标准实现更快的系统级集成。现有 IP 可以在设计中使用 RTL 或网表格式。有关更多信息，请参见 Vivado 设计套件用户指南：利用 IP 进行设计 （UG896）。

③、IP Subsystem Design（IP子系统设计）
The Vivado IP integrator environment enables you to stitch together various IP into IP subsystems using the AMBA® AXI4 interconnect protocol. You can interactively configure and connect IP using a block design style interface and easily connect entire interfaces by drawing DRC-correct connections similar to a schematic. Connecting the IP using standard interfaces saves time over traditional RTL-based connectivity. Connection automation is provided as well as a set of DRCs to ensure proper IP configuration and connectivity. These IP block designs are then validated, packaged, and treated as a single design source. Block designs can be used in a design
project or shared among other projects. The IP integrator environment is the main interface for embedded design and the AMD evaluation board interface. For more information, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).

Vivado IP 集成器环境使您能够使用 AMBA AXI4 互连协议将各种 IP 拼接到 IP 子系统中。您可以使用模块设计样式接口以交互方式配置和连接 IP，并通过绘制类似于原理图的 DRC 正确连接轻松连接整个接口。与传统的基于 RTL 的连接相比，使用标准接口连接 IP 可节省时间。提供连接自动化以及一组 DRC，以确保正确的 IP 配置和连接。然后对这些 IP 模块设计进行验证、封装，并将其视为单个设计源。块设计可以在设计项目中使用，也可以在其他项目之间共享。IP 集成器环境是嵌入式设计和 AMD 评估板接口的主接口。有关更多信息，请参见《Vivado 设计套件用户指南：使用 IP 集成器设计 IP 子系统 》（UG994）。

④、I/O and Clock Planning
The Vivado IDE provides an I/O pin planning environment that enables I/O port assignment either onto specific device package pins or onto internal die pads, and provides tables to let you design and analyze package and I/O-related data. Memory interfaces can be assigned interactively into specific I/O banks for optimal data flow. You can analyze the device and design-
related I/O data using the views and tables available in the Vivado pin planner. The tool also provides I/O DRC and simultaneous switching noise (SSN) analysis commands to validate your I/O assignments. For more information, see the Vivado Design Suite User Guide: I/O and Clock
Planning (UG899).
Vivado IDE 提供了一个 I/O 引脚规划环境，支持将 I/O 端口分配到特定器件封装引脚或内部芯片焊盘上，并提供表格，让您能够设计和分析封装和 I/O 相关数据。内存接口可以交互方式分配给特定的 I/O 组，以实现最佳数据流。您可以使用 Vivado 引脚规划器中提供的视图和表格分析器件和设计相关的 I/O 数据。该工具还提供 I/O DRC 和同步开关噪声 （SSN） 分析命令，以验证您的 I/O 分配。有关更多信息，请参见 Vivado 设计套件用户指南：I/O 和时钟规划 （UG899）。

⑤、AMD Platform Board Support
In the Vivado Design Suite, you can select an existing AMD evaluation platform board as a target for your design. In the platform board flow, all of the IP interfaces implemented on the target board are exposed to enable quick selection and configuration of the IP used in your design. The
resulting IP configuration parameters and physical board constraints, such as I/O standard and package pin constraints, are automatically assigned and proliferated throughout the flow.Connection automation enables quick connections to the selected IP. For more information see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
在 Vivado 设计套件中，您可以选择现有的 AMD 评估平台板作为设计的目标。在平台板流程中，目标板上实现的所有 IP 接口都公开，以便快速选择和配置设计中使用的 IP。由此产生的 IP 配置参数和物理板约束（如 I/O 标准和封装引脚约束）将在整个流程中自动分配和扩散。连接自动化可实现与所选 IP 的快速连接。有关更多信息，请参见《Vivado 设计套件用户指南：系统级设计入门级手册》（UG895）中的此链接。
⑥、Synthesis 综合
Vivado synthesis performs a global, or top-down synthesis of the overall RTL design.
Vivado 综合对整个 RTL 设计进行全局或自顶向下的综合。
However,by default, the Vivado Design Suite uses an out-of-context (OOC), or bottom-up design flow to synthesize IP cores from the AMD IP Catalog and block designs from the Vivado IP integrator.
但是，默认情况下，Vivado 设计套件使用脱离上下文 (OOC) 或自下而上的设计流程来综合 AMD IP 目录中的 IP 内核和 Vivado IP 集成器中的块设计。

You can also choose to synthesize specific modules of a hierarchical RTL design as OOC modules.This OOC flow lets you synthesize, implement, and analyze design modules of a hierarchical design, IP cores, or block designs, out of the context of, or independent from the top-level design. The OOC synthesized netlist is stored and used during top-level implementation to preserve results and reduce runtime. The OOC flow is an efficient technique for supporting hierarchical team design, synthesizing and implementing IP and IP subsystems, and managing modules of large complex designs.
您还可以选择将分层的 RTL 设计的特定模块综合为 OOC 模块。通过 OOC 流程，您可以综合、实现和分析分层设计、IP 核或块设计的设计模块，使其脱离顶层设计或独立于顶层设计。OOC 综合网表可在顶层实现过程中存储和使用，以保留结果并缩短运行时间。OOC 流程是支持分层团队设计、综合和实现 IP 和 IP 子系统以及管理大型复杂设计模块的高效技术。
For more information on the out-of-context design flow, see Out-of-Context Design Flow.

The Vivado Design Suite also supports the use of third-party synthesized netlists, including EDIF or structural Verilog. However, IP cores from the Vivado IP Catalog must be synthesized using Vivado synthesis, and are not supported for synthesis with a third-party synthesis tool. There are a few exceptions to this requirement, such as the memory IP for 7 series devices. Refer to the data sheet for a specific IP for more information.
Vivado 设计套件还支持使用第三方综合网表，包括 EDIF 或结构化 Verilog。但是，Vivado IP 目录中的 IP 核必须使用 Vivado 合成进行合成，不支持使用第三方合成工具进行综合。此要求有一些例外，例如 7 系列设备的内存 IP。有关详细信息，请参阅特定 IP 的数据手册。
Note: The ISE Netlist format (NGC) is supported for 7 series devices. It is not supported for AMD UltraScale™ and later devices.
注意：7 系列设备支持 ISE 网表格式 （NGC）。AMD UltraScale™ 及更高版本的设备不支持此功能。

⑦、Design Analysis and Simulation 设计分析与仿真
The Vivado Design Suite lets you analyze, verify, and modify the design at each stage of the design process. You can run design rule and design methodology checks, logic simulation, timing and power analysis to improve circuit performance. This analysis can be run after RTL elaboration,synthesis, and implementation. For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
Vivado 设计套件允许您在设计流程的每个阶段分析、验证和修改设计。您 可以运行设计规则和设计方法 检查、逻辑仿真、时序和功耗分析，以提高电路性能。分析可以在 RTL 分析、综合和实现之后进行。有关更多信息，请参见《Vivado 设计套件用户指南：设计分析和收敛技术》（UG906）。
The Vivado simulator enables you to run behavioral and structural logic simulation of the design at different stages of the design flow. The simulator supports Verilog and VHDL mixed-mode simulation, and results can be displayed in a waveform viewer integrated in the Vivado IDE. You can also use third-party simulators that can be integrated into and launched from the Vivado IDE.Refer to Running Logic Simulation for more information.
通过 Vivado 仿真器，您可以在设计流程的不同阶段对设计进行行为和结构逻辑仿真。仿真器支持 Verilog 和 VHDL 混合模式仿真，仿真结果可在 Vivado IDE 中集成的波形查看器中显示。您还可以使用第三方仿真器，这些仿真器可以集成到 Vivado IDE 中并从 Vivado IDE 中启动。更多信息请参阅运行逻辑仿真。

⑥、Placement and Routing
When the synthesized netlist is available, Vivado implementation provides all the features necessary to optimize, place and route the netlist onto the available device resources of the target part.
当综合网表可用时，Vivado 实现可提供所有必要功能，将网表优化、布局和布线到目标器件的可用器件资源上。
Vivado implementation works to satisfy the logical, physical, and timing constraints of the design.For challenging designs the Vivado IDE also provides advanced floorplanning capabilities to help drive improved implementation results.
Vivado 实现可满足设计的逻辑、物理和时序约束。对于具有挑战性的设计，Vivado IDE 还提供了高级平面规划功能，以帮助改进实现结果。对于具有挑战性的设计，Vivado IDE 还提供了高级平面规划功能，以帮助改进实现结果。
These include the ability to constrain specific logic into a particular area, or manually placing specific design elements and fixing them for subsequent implementation runs. For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
这些功能包括将特定逻辑限制在特定区域内，或手动放置特定设计元素并在后续实现运行中对其进行固定。有关详细信息，请参阅《Vivado 设计套件用户指南》： 设计分析和封闭技术 (UG906)。

⑦、Hardware Debug and Validation 硬件调试和验证
After implementation, the device can be programmed and then analyzed with the Vivado logic analyzer, or within the standalone Vivado Lab Edition environment. Debug signals can be identified in the RTL design, or inserted after synthesis and are processed throughout the flow.
实现后，可对器件进行编程，然后使用 Vivado 逻辑分析仪或在独立的 Vivado Lab Edition 环境中进行分析。调试信号可以在 RTL 设计中确定，也可以在综合后插入，并在整个流程中进行处理。

You can add debug cores to the RTL source files, to the synthesized netlist, or in an implemented design using the using the Engineering Change Order (ECO) flow.
You can also modify the nets connected to a debug probe, or route internal signals to a package pin for external probing using the ECO flow. For more information, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).
您可以使用工程变更单 (ECO) 流程将调试核添加到 RTL 源文件、综合网表或已实现的设计中。
您还可以修改连接到调试探针的网线，或使用 ECO 流程将内部信号路由到封装引脚以进行外部探测。有关详细信息，请参阅《Vivado 设计套件用户指南》： 编程和调试 (UG908)。

5、Alternate RTL-to-Bitstream Design Flows（替代RTL到比特流方式的设计流程）

略，大概是用其他的设计代替传统的方法，

High-Level Synthesis C-Based Design 基于 C语言的高层次综合

The C-based High-Level Synthesis (HLS) tools within the Vivado Design Suite enable you to describe various DSP functions in the design using C, C++, and SystemC. You create and validate the C code with the Vivado HLS tools. Use of higher-level languages allows you to abstract algorithmic descriptions, data type, specification, etc. You can create “what-if” scenarios using various parameters to optimize design performance and device area.
Vivado 设计套件中基于 C 的高级合成 (HLS) 工具使您能够使用 C、C++ 和 SystemC 描述设计中的各种 DSP 功能。您可以使用 Vivado HLS 工具创建和验证 C 代码。使用高级语言可以对算法描述、数据类型、规格等进行抽象。您可以使用各种参数创建 "假设 "场景，以优化设计性能和器件面积。

HLS lets you simulate the generated RTL directly from its design environment using C-based test benches and simulation. C-to-RTL synthesis transforms the C-based design into an RTL module that can be packaged and implemented as part of a larger RTL design, or instantiated into an IP
integrator block design.
HLS 可让您使用基于 C 的测试台和仿真，直接从设计环境中对生成的 RTL 进行仿真。C 到 RTL 综合可将基于 C 的设计转换为 RTL 模块，该模块可作为更大 RTL 设计的一部分打包和实现，或实例化为 IP集成块设计。

The HLS tool flow and features are described in the following resources:
• Vivado Design Suite User Guide: High-Level Synthesis (UG902)
• Vivado Design Suite Tutorial: High-Level Synthesis (UG871)

二、Understanding Use Models

1、Vivado Design Suite Use Models

推荐：在使用 AMD Vivado 工具开始首次设计之前，请查看 Vivado™ 设计套件用户指南：入门 （UG910） 中的信息。

Just as the Vivado supports many different design flows, the tools support several different use models depending on how you want to manage your design and interact with the Vivado tools.
正如 Vivado 支持许多不同的设计流程一样，这些工具支持多种不同的使用模式，具体取决于您希望如何管理设计以及与 Vivado 工具交互。本节将指导您完成一些必须做出的有关与 Vivado 工具交互的使用模式的决定。
This section will help guide you through some of the decisions that you must make about the use model you want to use for interacting with the Vivado tools.

Some of these decisions include:
• Are you a script or command-based user; or do you prefer working through a graphical user interface (GUI)? - 您是脚本或基于命令的用户，还是更喜欢通过图形用户界面（GUI）工作？See Working with the Vivado Integrated Design Environment (IDE) and Working with Tcl.
• Do you want the Vivado Design Suite to manage the design sources, status, and results by using a project structure; or would you prefer to quickly create and manage a design yourself?- 您是希望 Vivado 设计套件使用项目结构管理设计源、状态和结果，还是希望自己快速创建和管理设计？
See Understanding Project Mode and Non-Project Mode.
• Do you want to configure IP cores and contain them within a single design project for portability; or establish a remote repository of configured IP cores outside of the project for easier management across multiple projects?- 您是想配置 IP 内核并将其包含在单个设计项目中以实现可移植性，还是想在项目之外建立一个配置 IP 内核的远程存储库以方便跨多个项目的管理？
• Are you managing your source files inside a revision control system? See Interfacing with Revision Control Systems.
• Are you using third-party tools for synthesis or simulation? See Using Third-Party Design Software Tools.

• 您是否在版本控制系统中管理源文件？请参阅 “与修订控制系统对接”。
• 您是否使用第三方工具进行综合或仿真？请参阅使用第三方设计软件工具。

2、Working with the Vivado Integrated Design Environment (IDE)（使用vivado集成开发环境）

The Vivado Integrated Design Environment (IDE) can be used in both Project Mode and Non-Project Mode. The Vivado IDE provides an interface to assemble, implement, and validate your design and IP. Opening a design loads the current design netlist, applies design constraints, and fits the design onto the target device. The Vivado IDE allows you to visualize and interact with the design as shown in the following figure.
Vivado 集成设计环境 (IDE) 可在项目模式和非项目模式下使用。Vivado 集成设计环境提供了一个界面，用于组装、实现和验证您的设计和 IP。打开设计会加载当前设计网表、应用设计约束并将设计安装到目标器件上。Vivado IDE 允许您对设计进行可视化和交互，如下图所示。
When using Project Mode, the Vivado IDE provides an interface called Flow Navigator, that supports a push-button design flow. You can open designs after RTL elaboration, synthesis, or implementation and analyze the design, make changes to constraints, logic or device configuration, and implementation results. You can also use design checkpoints to save the
current state of any design.
使用 "项目模式 "时，Vivado IDE 提供一个名为 "流程导航器 "的界面，支持按钮式设计流程。您可以在 RTL 详细设计、综合或实现后打开设计，分析设计，更改约束、逻辑或器件配置以及实现结果。您还可以使用设计检查点来保存任何设计的当前状态。

有关 Vivado IDE 的更多信息，请参阅《Vivado 设计套件用户手册》、 有关 Vivado IDE 的更多信息，请参阅《Vivado 设计套件用户指南》： 使用 Vivado IDE (UG893)。

三种启动方式

①、Launching the Vivado IDE on Windows

Select Start → All Programs → Xilinx Design Tools → Vivado → Vivado .
Note: You can also double-click the Vivado IDE shortcut icon on your desktop.

TIP: You can right-click the Vivado IDE shortcut icon, and select Properties to update the Start In field.This makes it easier to locate the project file, log files, and journal files, which are written to the launch directory.
提示：您可以右键单击 Vivado IDE 快捷图标，然后选择 "属性 "以更新 "启动于 "字段。这样可以更轻松地找到写入启动目录的项目文件、日志文件和日志文件。
②、Launching the Vivado IDE from the Command Line on Windows or Linux
提示：要将 Vivado 工具路径添加到当前 shell/命令提示符，请运行
settings64.bat or settings64.sh from the <install_path>/Vivado/ directory

从命令行启动 Vivado 设计套件时，请将目录更改为您的项目目录，以便 Vivado 工具将其日志和日志文件写入您的项目目录。这样就可以根据需要轻松查找和查看这些文件。

建议：从您的项目目录启动 Vivado 设计套件，以便更轻松地找到写入启动目录的项目文件、日志文件和日志文件。（也就是先建立文件，再从文件处打开vivado）

③、Launching the Vivado IDE from the Vivado Design Suite Tcl Shell

When the Vivado Design Suite is running in Tcl mode, enter the following command at the Tcl command prompt to launch the Vivado IDE:
当 Vivado Design Suite 以 Tcl 模式运行时，在 Tcl 命令提示符下输入以下命令以启动 Vivado IDE：
start_gui

3、Working with Tcl（使用TCL语言）

All supported design flows and use models can be run using Tcl commands. You can use Tcl scripts to run the entire design flow, including design analysis and reporting, or to run parts of the design flow, such as design creation and synthesis. You can use either individual Tcl commands or saved scripts of Tcl commands.可以使用 Tcl 命令运行所有支持的设计流程和使用模型。您可以使用 Tcl 脚本运行整个设计流程，包括设计分析和报告，也可以运行部分设计流程，如设计创建和综合。您既可以使用单独的 Tcl 命令，也可以使用已保存的 Tcl 命令脚本。

If you prefer working directly with Tcl commands, you can interact with your design using a Vivado Design Suite Tcl shell, using the Tcl Console from within the Vivado IDE. For more information about using Tcl and Tcl scripting, see the Vivado Design Suite User Guide: Using Tcl Scripting (UG894) and Vivado Design Suite Tcl Command Reference Guide (UG835). For a step-by-
step tutorial that shows how to use Tcl in the Vivado tools, see the Vivado Design Suite Tutorial:Design Flows Overview (UG888).如果您更喜欢直接使用 Tcl 命令，则可以使用 Vivado IDE 中的 Tcl 控制台，使用 Vivado Design Suite Tcl shell 与您的设计进行交互。有关使用 Tcl 和 Tcl 脚本的更多信息，请参阅《Vivado Design Suite 用户指南》： 使用 Tcl 脚本 (UG894) 和 Vivado Design Suite Tcl 命令参考指南 (UG835)。有关如何使用 Tcl 脚本的逐步
教程，请参见《Vivado 设计套件教程：设计流程概述》(UG888)。

For more information on using a Tcl-based approach using either the Project Mode or Non-Project Mode, see Understanding Project Mode and Non-Project Mode.有关使用基于 Tcl 的项目模式或非项目模式的更多信息，请参阅了解项目模式和非项目模式。

启动脚本的方式有很多种：
①、

启动 Vivado Design Suite Tcl Shell
在 Linux 命令提示符或 Windows 命令提示符窗口中使用以下命令调用 Vivado Design Suite Tcl Shell
命令提示符或 Windows 命令提示符窗口中调用 Vivado Design Suite Tcl Shell：vivado -mode tcl
注：在 Windows 中，也可以选择开始 → 所有程序 → Xilinx Design Tools → Vivado → Vivado Tcl Shell
②、

使用批处理 Tcl 脚本启动 Vivado 工具
通过在调用工具时提供 Tcl 脚本，可以在批处理模式下使用 Vivado 工具。使用在 Linux 命令提示符或 Windows 命令提示符窗口中使用以下命令
提示窗口中使用以下命令：
vivado -mode batch -source <your_Tcl_script>
注意：在批处理模式下工作时，Vivado 工具会在运行指定脚本后退出。

③、Using the Vivado IDE with a Tcl Flow
When working with Tcl, you can still take advantage of the interactive GUI-based analysis and constraint definition capabilities in the Vivado IDE. You can open designs in the Vivado IDE at any stage of the design cycle, as described in Performing Design Analysis Using the Vivado IDE.You can also save the design database at any time as a checkpoint file, and open the checkpoint later as described in Using Design Checkpoints.

④、Using AMD Vivado Store 使用 AMD Vivado Store
The AMD Vivado Store enables you to download Tcl apps, board files, and example designs from AMD’s public GitHub repository. The download path for both boards and example designs can be defined in your Tool→Settings. Third-parties can also contribute to these repositories by submitting GitHub pull requests. For more information on submitting, please refer to the following document on the GitHub page.
通过 AMD Vivado Store，您可以从 AMD 公共 GitHub 存储库下载 Tcl 应用程序、电路板文件和示例设计。AMD 的公共 GitHub 存储库中下载 Tcl 应用程序和示例设计。电路板和示例设计的下载路径可在 Tool→Settings. Third-parties也可以通过以下方式为这些资源库做出贡献提交 GitHub 拉取请求。

（原文档提供了xilinx官方的github仓库，强烈建议看原文档！！！！！）
https://github.com/Xilinx/XilinxTclStore

有关提交的更多信息，请参阅 GitHub 页面上的以下文档。
• Tcl Store
• Board Store
• CED Store
⑤、AMD Tcl Apps
The AMD Tcl Store is an open source repository of Tcl code designed primarily for use in FPGA designs with the Vivado Design Suite. The Tcl Store provides access to multiple scripts and utilities contributed from different sources, which solve various issues and improve productivity.
You can install Tcl scripts and also contribute Tcl scripts to share your expertise with others. AMD Tcl Store 是 Tcl 代码的开放源代码库，主要用于使用 Vivado 设计套件进行 FPGA 设计。通过 Tcl Store 可以访问不同来源提供的多个脚本和实用程序，这些脚本和实用程序可解决各种问题并提高工作效率。您可以安装 Tcl 脚本，也可以贡献 Tcl 脚本，与他人分享您的专业知识。

For more information on working with Tcl scripts and the AMD Tcl Store, see the Vivado Design Suite User Guide: Using Tcl Scripting (UG894).

⑥、Board Files
Board files define external connectivity for Vivado. Board files information is available in the IP integrator when you select a board, as opposed to a part, when creating the project. Board interfaces can be enabled in the IP integrator by selecting the appropriate interface in the Boards tab in Vivado. For more information, see the Vivado Design Suite User Guide: Designing IP
Subsystems Using IP Integrator (UG994) and the Integrated Interlaken up to 150G LogiCORE IP Product Guide (PG169).
电路板文件定义了 Vivado 的外部连接。创建项目时，选择电路板（而非部件）时，IP 集成器中会显示电路板文件信息。在 Vivado 中的 "电路板 "选项卡中选择相应的接口，即可在 IP 集成器中启用电路板接口。有关详细信息，请参阅《Vivado 设计套件用户指南》： 使用 IP 集成器设计 IP子系统》（UG994）和《Integrated Interlaken up to 150G LogiCORE IP Product Guide》（PG169）。

4、Understanding Project Mode and Non-Project Mode（了解工程模式和非工程模式）

The Vivado Design Suite has two primary use models: Project Mode and Non-Project Mode.Both Project Mode and Non-Project Mode can be developed and used through either the Vivado IDE, or through Tcl commands and batch scripts. However, the Vivado IDE offers many benefits for the Project Mode, such as the Flow Navigator graphical workflow interface. Tcl commands are the simplest way to run the Non-Project Mode.
Vivado 设计套件有两种主要使用模式：项目模式和非项目模式： 项目模式和非项目模式均可通过 Vivado IDE 或 Tcl 命令和批脚本进行开发和使用。然而，Vivado IDE 为项目模式提供了许多优势，例如 Flow Navigator 图形工作流程界面。Tcl 命令是运行非项目模式的最简单方法。

Project Mode

The Vivado Design Suite takes advantage of a project based architecture to assemble, implement,and track the state of a design. This is referred to as Project Mode. In Project Mode, Vivado tools automatically manage your design flow and design data.Vivado 设计套件利用基于项目的架构来组装、实施和跟踪设计状态。这被称为 “项目模式”。在项目模式下，Vivado 工具会自动管理设计流程和设计数据。

TIP: The key advantage of Project Mode is that the Vivado Design Suite manages the entire design process,including dependency management, report generation, data storage, etc.提示：项目模式的主要优势在于 Vivado Design Suite 可管理整个设计流程，包括依赖关系管理、报告生成、数据存储等。

When working in Project Mode, the Vivado Design Suite creates a directory structure on disk in order to manage design source files, either locally or remotely, and manage changes and updates to the source files.在项目模式下工作时，Vivado Design Suite 会在磁盘上创建一个目录结构，以便在本地或远程管理设计源文件，并管理源文件的更改和更新。

Note: Certain operating systems (for example, Microsoft Windows) restrict the number of characters (such as 256) that can be used for the file path and file name. If your operating system has such a limitation,AMD recommends that you create projects closer to the drive root to keep file paths and names as short as possible.注意：某些操作系统（如 Microsoft Windows）限制文件路径和文件名可使用的字符数（如 256）。如果您的操作系统有此限制，AMD 建议您在靠近驱动器根目录的位置创建项目，以尽可能缩短文件路径和文件名。

The project infrastructure is also used to manage the automated synthesis and implementation runs, track run status, and store synthesis and implementation results and reports. For example:项目基础设施还用于管理自动合成和实施运行、跟踪运行状态、存储合成和实施结果及报告。例如

• If you modify an HDL source after synthesis, the Vivado Design Suite identifies the current results as out-of-date, and prompts you for re-synthesis.
• If you modify design constraints, the Vivado tools prompt you to either re-synthesize, re-implement, or both.
• After routing is completed, the Vivado tool automatically generates timing, DRC, methodology, and power reports.
• The entire design flow can be run with a single click within the Vivado

• 如果您在综合后修改 HDL 源，Vivado 设计套件会将当前结果识别为过时，并提示您重新综合。
• 如果修改了设计约束，Vivado 工具会提示您重新综合、重新实现或两者兼而有之。
• 布线完成后，Vivado 工具会自动生成时序、DRC、方法和功耗报告。
• 只需在 Vivado 系统中点击一下鼠标，即可运行整个设计流程。

Non-Project Mode

Alternatively, you can choose an in-memory compilation flow in which you manage sources and the design process yourself, known as Non-Project Mode. In-memory compilation enables project settings to be applied to Non-Project based designs. In Non-Project Mode, you manage design sources and the design process yourself using Tcl commands or scripts. The key advantage is that you have full control over each step of the flow.另外，您也可以选择内存编译流程，在此流程中，您可以自行管理源代码和设计流程，即所谓的非项目模式。内存编译可将项目设置应用于基于非项目的设计。在非项目模式下，您可以使用 Tcl 命令或脚本自行管理设计源和设计流程。其主要优势在于，您可以完全控制流程的每一步。

When working in Non-Project Mode, source files are read from their current locations, such as from a revision control system, and the design is compiled through the flow in memory. You can run each design step individually using Tcl commands. You can also use Tcl commands to set design parameters and implementation options.在 "非项目模式 "下工作时，源文件从其当前位置读取，例如从版本控制系统读取，设计在内存中按流程编译。您可以使用 Tcl 命令单独运行每个设计步骤。您还可以使用 Tcl 命令设置设计参数和实现选项。

You can save design checkpoints and create reports at any stage of the design process. Each implementation step can be tailored to meet specific design challenges, and you can analyze results after each design step. In addition, you can open the Vivado IDE at any point for design analysis and constraints assignment.您可以保存设计检查点，并在设计过程的任何阶段创建报告。每个实现步骤都可以量身定制，以应对特定的设计挑战，您还可以在每个设计步骤后分析结果。此外，您还可以在任何时候打开 Vivado IDE 进行设计分析和约束分配。

In Non-Project Mode, each design step is controlled using Tcl commands. For example:
• If you modify an HDL file after synthesis, you must remember to rerun synthesis to update the in-memory netlist.
• If you want a timing report after routing, you must explicitly generate the timing report when routing completes.
• Design parameters and implementation options are set using Tcl commands and parameters.
• You can save design checkpoints and create reports at any stage of the design process using Tcl.
在非项目模式下，每个设计步骤都由 Tcl 命令控制。例如

• 如果在综合后修改 HDL 文件，必须记住重新运行综合以更新内存网表。
• 如果在布线后需要时序报告，则必须在布线完成后明确生成时序报告。
• 设计参数和实现选项使用 Tcl 命令和参数进行设置。
• 您可以在设计过程的任何阶段使用 Tcl 保存设计检查点并创建报告。

As the design flow progresses, the representation of the design is retained in memory in the Vivado Design Suite. Non-Project Mode discards the in-memory design after each session and only writes data to disk that you instruct it to. For more information on Non-Project Mode, see Chapter 4: Using Non-Project Mode**.随着设计流程的进行，设计的表示将保留在 Vivado 设计套件的内存中。非项目模式会在每个会话结束后丢弃内存中的设计，只将您指示的数据写入磁盘。**有关非项目模式的更多信息，请参见第 4 章：使用非项目模式。

Feature Differences

In Project Mode, the Vivado IDE tracks the history of the design and stores pertinent design
information. However, because many features are automated, you have less control in the default
flow. For example, only a standard set of report files is generated with each run. However,
through Tcl commands or scripting, you have access to customize the flow and features of the
tool in Project Mode.在项目模式下，Vivado IDE 会跟踪设计的历史并存储相关的设计信息。但是，由于许多功能都是自动执行的，因此在默认流程中您的控制能力较弱。例如，每次运行只生成一组标准报告文件。但是通过 Tcl 命令或脚本，您可以在项目模式下自定义流程和工具功能。

The following automated features are only available when using Project Mode:
以下自动功能仅在使用项目模式时可用：
• Out-of-the-box design flow- 开箱即用的设计流程
• Easy-to-use, push-button interface- 易于使用的按钮式界面
• Powerful Tcl scripting language for customization- 用于定制的强大 Tcl 脚本语言
• Source file management and status- 源文件管理和状态
• Automatically generated standard reports- 自动生成标准报告
• Storage and reuse of tool settings and design configuration- 工具设置和设计配置的存储和重用
• Experimentation with multiple synthesis and implementation runs- 多个综合和实现运行实验
• Run results management and status- 运行结果管理和状态

Non-Project Mode, is more of a compilation methodology where you have complete control over
every action executed through a Tcl command. This is a fully customizable design flow suited to
specific designers looking for control and batch processing. All of the processing is done in
memory, so no files or reports are generated automatically. Each time you compile the design,
you must define all of the sources, set all tool and design configuration parameters, launch all
implementation commands, and generate report files. This can be accomplished using a Tcl run
script, because a project is not created on disk, source files remain in their original locations and
design output is only created when and where you specify. This method provides you with all of
the power of Tcl commands and full control over the entire design process. Many users prefer
this batch compilation style interaction with the tools and the design data.
非项目模式更像是一种编译方法，您可以完全控制通过 Tcl 命令执行的每一个操作。通过 Tcl 命令执行的每个操作。这是一种完全可定制的设计流程，适合于设计人员寻求控制和批量处理。所有处理都在内存中完成。因此不会自动生成文件或报告。每次编译设计时都必须定义所有源、设置所有工具和设计配置参数、启动所有执行命令并生成报告文件。执行命令并生成报告文件。这可以使用 Tcl 运行脚本来完成，因为项目不在磁盘上创建，源文件保留在其原始位置，而设计输出仅在何时何地创建。设计输出仅在您指定的时间和地点创建。这种方法为您提供了所有Tcl 命令的所有功能，并完全控制整个设计过程。许多用户更喜欢这种批量编译方式可以与工具和设计数据进行交互。

The following table summarizes the feature differences between Project Mode and Non-Project
Mode.下表总结了项目模式和非项目模式之间的功能差异。

Command Differences

Tcl commands vary depending on the mode you use, and the resulting Tcl run scripts for each
mode are different. In Non-Project Mode, all operations and tool settings require individual Tcl
commands, including setting tool options, running implementation commands, generating
reports, and writing design checkpoints. In Project Mode, wrapper commands are used around
the individual synthesis, implementation, and reporting commands.Tcl 命令会因使用的模式不同而不同，每种模式下产生的 Tcl 运行脚本也不同。也不同。在非项目模式下，所有操作和工具设置都需要单独的 Tcl
命令，包括设置工具选项、运行执行命令、生成报告和编写设计检查点。在 "项目模式 "下，封装命令用于围绕综合、执行和报告命令的封装命令。
For example, in Project Mode, you add sources to the project for management using the
add_files Tcl commands. Sources can be copied into the project to maintain a separate version
within the project directory structure or can be referenced remotely. In Non-Project Mode, you
use the read_verilog, read_vhdl, read_xdc, and read_* Tcl commands to read the various types of sources from their current location.例如，在项目模式下，您可以使用add_files Tcl 命令将源代码添加到项目中进行管理。源代码可以复制到项目中，以便在项目目录结构中保持独立版本，也可以远程引用。或远程引用。在非项目模式下，可使用 read_verilog、read_vhdl、read_xdc 和 read_* Tcl 命令从当前位置读取各类源代码。从当前位置读取各种类型的源代码。
In Project Mode, the launch_runs command launches the tools with preconfigured run strategies and generates standard reports. This enables consolidation of implementation commands, standard reporting, use of run strategies, and run status tracking. However, you can also run custom Tcl commands before or after each step of the design process. Run results are automatically stored and managed within the project. In Non-Project Mode, individual commands must be run, such as opt_design, place_design, and route_design.在项目模式下，launch_runs 命令使用预先配置的运行策略启动工具，并生成标准报告。这样就能整合执行命令、标准报告、使用运行策略和跟踪运行状态。不过，您也可以也可以在设计流程的每个步骤之前或之后运行自定义 Tcl 命令。运行结果自动存储并管理在项目中。在非项目模式下，必须运行单个命令，例如必须运行，如 opt_design、place_design 和route_design。
Many Tcl commands can be used in either mode, such as the reporting commands. In some cases,
Tcl commands are specific to either Project Mode or Non-Project Mode. Commands that are
specific to one mode must not be mixed when creating scripts. For example, if you are using the
Project Mode you must not use base-level commands such as synth_design, because these
are specific to Non-Project Mode. If you use Non-Project Mode commands in Project Mode, the
database is not updated with status information and reports are not automatically generated.
Note: Project Mode includes GUI operations, which result in a Tcl command being executed in most cases.
许多 Tcl 命令可以在两种模式下使用，例如报告命令。在某些情况下Tcl 命令专用于项目模式或非项目模式。在混合使用在创建脚本时不得混合使用。例如，如果使用项目模式，就不能使用 synth_design 等基础级命令，因为这些命令是非项目模式专用的。是非项目模式的专用命令。如果在项目模式下使用非项目模式命令，数据库中的状态信息将不会更新。数据库不会更新状态信息，也不会自动生成报告。
注意：项目模式包括图形用户界面操作，在大多数情况下会执行 Tcl 命令。

The Tcl commands appear in the Vivado IDE Tcl Console and are also captured in the vivado.jou file.
You can use this file to develop scripts for use with either mode.The following figure shows the difference between Project Mode and Non-Project Mode Tcl
commands.Tcl 命令会显示在 Vivado IDE Tcl 控制台中，也会捕获到 vivado.jou 文件中。您可以使用该文件来开发脚本，以便在任一模式下使用。下图显示了项目模式和非项目模式 Tcl命令的区别。

5、Using Third-Party Design Software Tools（使用第三方设计软件工具）

AMD has strategic partnerships with several third-party design tool suppliers. The following
software solutions include synthesis and simulation tools only.AMD 与多家第三方设计工具供应商建立了战略合作伙伴关系。以下软件解决方案仅包括综合和仿真工具。

Running Logic Synthesis

The AMD FPGA logic synthesis tools supplied by Synopsys and Mentor Graphics are supported
for use with the Vivado Design Suite. In the Vivado Design Suite, you can import the synthesized
netlists in structural Verilog or EDIF format for use during implementation. In addition, you can
use the constraints (SDC or XDC) output by the logic synthesis tools in the Vivado Design Suite.
All AMD IP and Block Designs use Vivado Synthesis. Use of third party synthesis for AMD IP or
IP integrator block designs is not supported, with a few exceptions, such as the memory IP for 7
series devices. Refer to the data sheet for a specific IP for more information.支持由 Synopsys 和 Mentor Graphics 提供的 AMD FPGA 逻辑综合工具，可与 Vivado 设计套件一起使用。支持与 Vivado 设计套件一起使用。在 Vivado 设计套件中，您可以导入以结构 Verilog 或 EDIF 格式合成的在 Vivado 设计套件中，您可以导入结构 Verilog 或 EDIF 格式的综合网表，以便在实现过程中使用。此外，您还可以使用 Vivado 设计套件中逻辑综合工具输出的约束（SDC 或 XDC）。所有 AMD IP 和块设计都使用 Vivado 综合。不支持对 AMD IP 或 IP 集成块设计使用第三方合成。不支持对 AMD IP 或 IP 集成块设计使用第三方综合，只有少数例外，如 7系列器件的内存 IP。有关详细信息，请参阅特定 IP 的数据表。

Running Logic Simulation

Logic simulation tools supplied by Mentor Graphics, Cadence, Aldec, and Synopsys are integrated
and can be launched directly from the Vivado IDE. Netlists can also be produced for all supported
third-party logic simulators. From the Vivado Design Suite, you can export complete Verilog or
VHDL netlists at any stage of the design flow for use with third-party simulators. In addition, you
can export structural netlists with post-implementation delays in standard delay format (SDF) for
use in third-party timing simulation. The Vivado Design Suite also generates simulation scripts for
enterprise users. Using the scripts and compiled libraries, enterprise users can run the simulation
without the Vivado Design Suite environment.集成了 Mentor Graphics、Cadence、Aldec 和 Synopsys 提供的逻辑仿真工具，可直接从 Vivado IDE 启动。还可以为所有支持的第三方逻辑仿真器生成网表。您可以从 Vivado 设计套件中导出完整的 Verilog 或VHDL 网表，供第三方仿真器使用。此外，您还可以以标准延迟格式 (SDF) 导出带有实现后延迟的结构网表，以便在第三方时序仿真中使用。Vivado 设计套件还可为企业用户生成仿真脚本。企业用户可使用脚本和编译库运行仿真，而无需 Vivado Design Suite 环境。。

VIDEO: For more information, see the Vivado Design Suite QuickTake Video: Simulating with Cadence IES in Vivado and Vivado Design Suite QuickTake Video: Simulating with Synopsys VCS in Vivado.

Note: Some AMD IP provides RTL sources in only Verilog or VHDL format. After synthesis, structural
netlists can be created in either language.
视频： 有关详细信息，请参阅 Vivado Design Suite QuickTake 视频： 在 Vivado 中使用 Cadence IES 仿真和 Vivado Design Suite QuickTake 视频： 在 Vivado 中使用 Synopsys VCS 仿真。
注：某些 AMD IP 仅提供 Verilog 或 VHDL 格式的 RTL 源。综合后，结构网表可以用两种语言创建。

6、Interfacing with PCB Designers

The I/O planning process is critical to high-performing systems.I/O 规划流程对高性能系统至关重要。
Printed circuit board (PCB)designers are often concerned about the relationship and orientation of the FPGA on the PCB.印刷电路板（PCB）设计人员通常会关注 FPGA 在 PCB 上的关系和方向。These large ball grid array (BGA) devices are often the most difficult routing challenge a PCB designer faces. 这些大型球栅阵列 (BGA) 器件通常是 PCB 设计师面临的最困难的布线挑战。Additional concerns include critical interface routing, location of power rails, and signal integrity. 设计人员面临的最困难的布线挑战。其他需要考虑的问题还包括关键接口布线、电源轨位置和信号完整性。

A close collaboration between FPGA and PCB designers can help address these design challenges.
FPGA 和 PCB 设计人员之间的密切合作有助于解决这些设计难题。The Vivado IDE enables the designer to visualize the relationship between the physical package pins and the internal die pads to optimize the system-level interconnect.Vivado IDE 使设计人员能够可视化物理封装引脚与内部芯片焊盘之间的关系，从而优化系统级互连。
The Vivado Design Suite has several methods to pass design information between the FPGA,
PCB, and system design domains. Vivado 设计套件有多种方法在 FPGA、PCB 和系统设计域之间传递设计信息。

I/O pin configuration can be passed back and forth using a comma separated value (CSV) spreadsheet, RTL header, or XDC file.I/O 引脚配置可以使用逗号分隔值 (CSV) 电子表格、RTL 头文件或 XDC 文件来回传递 I/O 引脚配置。
The CSV spreadsheet contains additional package and I/O information that can be used for a variety of PCB design tasks, such as matched length connections and power connections.CSV 电子表格包含额外的封装和 I/O 信息，可用于各种 PCB 设计任务，如匹配长度连接和电源连接。
An I/O Buffer Information Specification (IBIS) model can also be exported from the Vivado IDE for use in signal integrity analysis on the PCB.还可从 Vivado IDE 导出 I/O 缓冲器信息规范 (IBIS) 模型，用于 PCB 上的信号完整性分析。

For more information see:
• Vivado Design Suite User Guide: I/O and Clock Planning (UG899)- Vivado 设计套件用户指南： I/O 和时钟规划 (UG899)
• Vivado Design Suite QuickTake Video: I/O Planning Overview- Vivado 设计套件 QuickTake 视频： I/O 规划概述
• Vivado Design Hub: I/O and Clock Planning Vivado Design Hub： I/O 和时钟规划

三、Using Project Mode（工程模式）

In Project Mode, the AMD Vivado™ Design Suite creates a project directory structure and
automatically manages your source files, constraints, IP data, synthesis and implementation run
results, and reports. In this mode, the Vivado Design Suite also manages and reports on the
status of the source files, configuration, and the state of the design.在项目模式下，AMD Vivado™ 设计套件会创建一个项目目录结构并自动管理源文件、约束、IP 数据、综合和实现运行结果以及报告。在此模式下，Vivado 设计套件还可管理和报告源文件的状态、配置和设计状态。

In the Vivado IDE, you can use the Flow Navigator (shown in the following figure) to launch predefined design flow steps, such as synthesis and implementation.在 Vivado IDE 中，您可以使用流程导航器（如下图所示）启动预定义的设计流程步骤，如综合和实现。
When you click Generate Bitstream or Generate Device Image for AMD Versal™ adaptive SoC, the Vivado IDE ensures that the design is synthesized and implemented with the most current design sources and generates a bitstream file. The environment provides an intuitive push button design flow and also offers advanced design management and analysis features. 单击生成比特流或为 AMD Versal™ 自适应 SoC 生成器件映像时，Vivado IDE 将确保设计以最符合实际的方式综合和实现。该环境提供直观的按钮式设计流程，还提供先进的设计管理和分析功能。还提供先进的设计管理和分析功能。

Runs are launched with wrapper Tcl scripts that consolidate the various implementation commands and automatically generates standard reports. You can use various run strategies to address different design challenges, such as routing density and timing closure. You can also simultaneously launch multiple
implementation runs to see which will achieve the best results.运行是通过封装Tcl 脚本启动运行，这些脚本整合了各种执行命令，并自动生成标准报告。您可以使用各种运行策略来应对不同的设计挑战，如
布线密度和时序闭合。您还可以同时启动多个实施运行，看看哪种运行策略能达到最佳效果。

Note: Run strategies only apply to Project Mode. In Non-Project Mode, all directives and command options must be set manually.注意：运行策略仅适用于项目模式。在非项目模式下，所有指令和命令选项都必须手动设置。

You can run Project Mode using the Vivado IDE or using Tcl commands or scripts. In addition,
you can alternate between using the Vivado IDE and Tcl within a project. When you open or
create projects in the Vivado IDE, you are presented with the current state of the design, run
results, and previously generated reports and messages. You can create or modify sources, apply
constraints and debug information, configure tool settings, and perform design tasks.您可以使用 Vivado IDE 或 Tcl 命令或脚本运行项目模式。此外、您还可以在项目中交替使用 Vivado IDE 和 Tcl。当您在 Vivado IDE 中打开或在 Vivado IDE 中打开或创建项目时，会显示设计的当前状态、运行结果以及先前生成的报告和消息。结果以及之前生成的报告和信息。您可以创建或修改源代码、应用约束和调试信息、配置工具设置并执行设计任务。

RECOMMENDED: Project Mode is the easiest way to get acquainted with features of the Vivado tools
and AMD recommendations.建议：项目模式是熟悉 Vivado 工具功能和 AMD 建议的最简单方法。

Vivado has the unique capability to open the design at various stages of the design flow. You can
open designs for analysis and constraints definition after RTL elaboration, synthesis, and implementation. 具有在设计流程的各个阶段打开设计的独特功能。您可以在 RTL 详细电路、综合和实现之后打开设计进行分析和约束定义。

When you open a design, the Vivado tools compile the netlist and constraints against the target device and show the design in the Vivado IDE. After you open the design, you can use a variety of analysis and reporting features to analyze the design using different criteria and viewpoints. You can also apply and save constraint and design changes.Vivado 当您打开设计时，Vivado 工具会根据目标器件编译网表和约束，并在 Vivado 的设计流程图中显示设计。打开设计后可以使用各种分析和报告功能，以不同的标准和视角分析设计。您还可以应用和保存约束和设计变更。

For moreinformation, see Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

1、Project Mode Advantages（工程模式优点）

Project Mode has the following advantages:
• Automatically manages project status, HDL sources, constraint files, IP cores and block
designs.- 自动管理项目状态、HDL 源、约束文件、IP 核和块设计。
• Generates and stores synthesis and implementation results - 生成并存储综合和实现结果
• Includes advanced design analysis capabilities, including cross probing from implementation
results to RTL source files - 包含高级设计分析功能，包括从实现结果到 RTL 源文件的交叉探测
• Automates setting command options using run strategies and generates standard reports

• 使用运行策略自动设置命令选项并生成标准报告
  • Supports the creation of multiple runs to configure and explore available constraint or command options- 支持创建多个运行，以配置和探索可用的约束或命令选项

2、Creating Projects（创建工程）

The Vivado Design Suite supports different types of projects for different design purposes. For
example, you can create a project with RTL sources or synthesized netlists from third-party
synthesis providers. You can also create empty I/O planning projects to enable device exploration
and early pin planning. The Vivado IDE only displays commands relevant to the selected project type.
Vivado 设计套件支持用于不同设计目的的不同类型的项目。例如，您可以使用第三方综合提供商提供的 RTL 源或综合网表创建项目。您还可以创建空的 I/O 规划项目，以便进行器件探索和早期引脚规划。Vivado IDE 只显示与所选项目类型相关的命令。

In the Vivado IDE, the Create Project wizard walks you through the process of creating a project.
The wizard enables you to define the project, including the project name, the location in which to
store the project, the project type (for example, RTL, netlist, and so forth), and the target part.在 Vivado IDE 中，创建项目向导将引导您完成创建项目的过程。该向导可让您定义项目，包括项目名称、项目存储位置、项目类型（如 RTL、网表等）和目标器件。
You can add different types of sources, such as RTL, IP, Block designs, XDC or SDC constraints,
simulation test benches, DSP modules from System Generator as IP, or Vivado High-Level
Synthesis (HLS), and design documentation.您可以添加不同类型的源，如 RTL、IP、块设计、XDC 或 SDC 约束、仿真测试台、来自 System Generator 作为 IP 的 DSP 模块或 Vivado 高级合成 (HLS) 的 DSP 模块以及设计文档。

When you select sources, you can determine whether to reference the source in its original location or to copy the source into the project directory. The Vivado Design Suite tracks the time and date stamp of each file and report status.If files are modified, you are alerted to out-of-date source or design status.
选择源时，可以决定是在原始位置引用源代码，还是将源代码复制到项目目录中。Vivado 设计套件会跟踪每个文件的时间和日期戳并报告状态。如果文件被修改，则会提醒您源文件或设计状态已过期。

For more information,see the Vivado Design Suite User Guide: System-Level Design Entry (UG895).

CAUTION! The Windows operating system has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use the shortest possible names and directory locations when creating projects, defining IP or managed IP projects, or creating block designs.注意！Windows 操作系统对路径长度有 260 个字符的限制，这会影响 Vivado 工具。为避免这一问题，在创建项目、定义 IP 或受管 IP 项目或创建块设计时，请使用尽可能短的名称和目录位置。

Different Types of Projects

The Vivado Design Suite allows for different design entry points depending on your source file
types and design tasks. Following are the different types of projects you can use to facilitate
those tasks:根据源文件类型和设计任务的不同，Vivado 设计套件允许不同的设计入口点。以下是您可用于促进这些任务的不同类型的项目这些任务：

• RTL Project: You can add RTL source files and constraints, configure IP with the Vivado IP
catalog, create IP subsystems with the Vivado IP integrator, synthesize and implement the
design, and perform design planning and analysis.
• Post-Synthesis Project: You can import third-party netlists, implement the design, and
perform design planning and analysis.
• I/O Planning Project: You can create an empty project for use with early I/O planning and
device exploration prior to having RTL sources.
• Imported Project: You can import existing project sources from the ISE Design Suite, Xilinx
Synthesis Technology (XST), or Synopsys Synplify.
• Example Project: You can explore several example projects, including example AMD Zynq™
7000 SoC or MicroBlaze™ embedded designs with available AMD evaluation boards.
• DFx: You can dynamically reconfigure an operating FPGA design by loading a partial bitstream
file to modify reconfigurable regions of the device.

• RTL 项目： 您可以添加 RTL 源文件和约束，使用 Vivado IP 目录创建 IP 子系统,综合和实现设计，以及执行设计规划和分析。
• 综合后项目： 您可以导入第三方网表、实现设计并执行设计规划和分析。
• I/O 规划项目： 您可以创建一个空项目，用于在有 RTL 源之前进行早期 I/O 规划和器件探索。
• 导入项目： 您可以从 ISE 设计套件、Xilinx合成技术 (XST) 或 Synopsys Synplify 中导入现有项目源。
• 示例项目： 您可以探索多个示例项目，包括 AMD Zynq™7000 SoC 或 MicroBlaze™ 嵌入式设计。
• DFx： 您可以通过加载部分比特流文件，动态地重新配置正在运行的 FPGA 设计。

Managing Source Files in Project Mode

In Project Mode, source management is performed by the project infrastructure. The Vivado IDE
manages different types of sources independently, including RTL design sources, IP, simulation
sources, and constraint sources. It uses the concept of a source set to enable multiple versions of
simulation or design constraints sets. This enables you to manage and experiment with different
sets of design constraints in one design project. The Vivado IDE also uses the same approach for
simulation, enabling management of module-level simulation sets for simulating different parts of
the design.在项目模式下，源代码管理由项目基础架构执行。Vivado IDE独立管理不同类型的源，包括 RTL 设计源、IP、仿真源和约束源。它使用源集的概念来启用多个版本的仿真或设计约束集。这样，您就可以在一个设计约束中管理和试验不同的设计约束集。Vivado IDE 对仿真也采用了相同的方法管理模块级仿真集，以仿真设计的不同部分。

When adding sources, you can reference sources from remote locations or copy sources locally
into the project directory structure. Sources can be read from any network accessible location.
With either approach, the Vivado IDE tracks the time and date stamps on the files to check for
updates. If source files are modified, the Vivado IDE changes the project status to indicate whether synthesis or implementation runs are out of date. Sources with read-only permissions are processed accordingly.添加源代码时，可以引用远程位置的源代码，也可以将本地源代码复制到项目目录结构中。可以从任何网络可访问位置读取源代码。
无论采用哪种方法，Vivado IDE 都会跟踪文件上的时间和日期戳，以检查是否有更新。如果源文件被修改，Vivado IDE 会更改项目状态，以显示综合或实现运行是否过时。具有只读权限的源文件进行相应处理。

When adding sources in the Vivado IDE, RTL files can optionally be scanned to look for include
files or other global source files that might be in the source directory. All source file types within
a specified directory or directory tree can be added with the File → Add Sources command. The
Vivado IDE scans directories and subdirectories and imports any file with an extension matching
the set of known sources types.在 Vivado IDE 中添加源代码时，可以选择扫描 RTL 文件，以查找源代码目录中可能存在的包含文件或其他全局源文件。指定目录或目录树中的所有源文件类型可使用文件 → 添加源代码命令添加指定目录或目录树中的所有源文件类型。Vivado IDE 会扫描目录和子目录，并导入扩展名与已知源类型集相匹配的任何文件。

After sources are added to a project, the compilation order and logic hierarchy is derived and
displayed in the Sources window. This can help you to identify malformed RTL or missing
modules. The Messages window shows messages related to the RTL compilation, and you can
cross probe from the messages to the RTL sources. In addition, source files can be enabled and
disabled to allow for control over configuration.将源代码添加到项目后，编译顺序和逻辑层次结构将被导出并显示在 "源代码 "窗口中。这可以帮助您识别畸形的 RTL 或丢失的模块。消息窗口显示与 RTL 编译相关的消息，您可以从消息到 RTL 源进行交叉探测。此外，还可启用和禁用源文件，以便控制配置。

Using Remote, Read-Only Sources

The Vivado Design Suite can utilize remote source files when creating projects or when read in
Non-Project Mode. Source files can be read-only, which compiles the files in memory but does
not allow changes to be saved to the original files. Source files can be saved to a different
location if required.Vivado 设计套件可以在创建项目时或在非项目模式下读取远程源文件。源文件可以只读，即在内存中编译文件，但不允许将更改保存到原始文件中。如果需要，源文件可以保存到不同的位置。

Archiving Projects 存档项目

In the Vivado IDE, select File → Project → Archive to create a ZIP file for the entire project,
including the source files, IP, design configuration, and optionally the run result data. If the
project uses remote sources, the files are copied into the project locally to ensure that the
archived project includes all files.在 Vivado IDE 中，选择文件 → 项目 → 存档，创建整个项目的 ZIP 文件、包括源文件、IP、设计配置和可选的运行结果数据。如果项目使用远程源，文件将被本地复制到项目中，以确保归档项目包含所有文件。

Creating a Tcl Script to Recreate the Project创建 Tcl 脚本以重新创建项目

In the Vivado IDE, the File → Project → Write Tcl command creates a Tcl script you can run to
recreate the entire project, including the source files, IP, and design configuration. You can check
this script into a source control system in place of the project directory structure.在 Vivado IDE 中，"文件"→"项目"→"写 Tcl "命令可创建一个 Tcl 脚本，您可以运行该脚本来重新创建整个项目，包括源文件、IP 和设计配置。您可以在该脚本，以代替项目目录结构。

Working with a Revision Control System使用版本控制系统

Many design teams use source management systems to store various design configurations and
revisions. There are multiple commercially available systems, such as Revision Control System
(RCS), Concurrent Versions System (CVS), Subversion (SVN), ClearCase, Perforce, Git, BitKeeper,
and many others. The Vivado tools can interact with all such systems. The Vivado Design Suite
uses and produces files throughout the design flow that you can manage with a revision control
system. For more information on working with revision control software, refer to Source
Management and Revision Control Recommendations.
许多设计团队使用源代码管理系统来存储各种设计配置和修订。市场上有多种可用的系统，如修订控制系统(RCS)、并发版本系统 (CVS)、Subversion (SVN)、ClearCase、Perforce、Git、BitKeeper 等。Vivado 工具可与所有这些系统交互。Vivado 设计套件在整个设计流程中使用并生成文件，您可以使用修订控制系统来管理这些文件。有关使用修订控制软件的更多信息，请参阅源代码管理和修订控制建议。

VIDEO: For information on best practices when using revision control systems with the Vivado tools, see
the Vivado Design Suite QuickTake Video: Using Vivado Design Suite with Revision Control.视频： 有关在 Vivado 工具中使用修订控制系统的最佳实践的信息，请参阅Vivado Design Suite QuickTake 视频： 将 Vivado Design Suite 与版本控制系统结合使用。

3、Understanding the Flow Navigator（了解流程导航器）

Understanding the Flow Navigator

The Flow Navigator (shown in the following figure) provides control over the major design
process tasks, such as project configuration, synthesis, implementation, and bitstream generation.
The commands and options available in the Flow Navigator depend on the status of the design.
Unavailable steps are grayed out until required design tasks are completed.流程导航器（如下图所示）可控制主要设计流程任务，如项目配置、综合、实现和位流生成。流程导航器中可用的命令和选项取决于设计的状态。在所需的设计任务完成之前，不可用的步骤将显示为灰色。

The Flow Navigator (shown in the following figure) differs when working with projects created
with third-party netlists. For example, system-level design entry, IP, and synthesis options are not
available.在处理使用第三方网表创建的项目时，流程导航器（如下图所示）有所不同。例如，没有系统级设计输入、IP 和综合选项可用。

As the design tasks complete, you can analyze the RTL by performing Linting on it and specifying
the waive-specific violations in the current design.
After cleaning up the design, you can open the resulting designs to analyze results and apply constraints. In the Flow Navigator, click Open Elaborated Design, Open Synthesized Design, or Open Implemented Design.

For more information, see Opening Designs to Perform Design Analysis and Constraints Definition.

When you open a design, the Flow Navigator shows a set of commonly used commands for the
applicable phase of the design flow. Selecting any of these commands in the Flow Navigator
opens the design, if it is not already opened, and performs the operation. For example, the following figure shows the commands related to synthesis
随着设计任务的完成，您可以对 RTL 执行 Linting 分析，并在当前设计中指定当前设计中特定于放弃的违规行为。
清理设计后，您可以打开分析结果并应用约束。在流程导航器中，单击打开详细设计、打开合成设计或打开已实现设计。
有关更多更多信息，请参阅打开设计以执行设计分析和约束定义。

打开设计时，"流程导航器 "会显示设计流程适用阶段的一组常用命令。在流程导航器中选择任何这些命令
将打开设计（如果尚未打开）并执行相关操作。例如下图显示了与综合有关的命令。
.

4、Performing System-Level Design Entry（执行系统级设计输入）

Automated Hierarchical Source File Compilation and Management
自动分层源文件编译和管理

The Vivado IDE Sources window (shown in the following figure) provides automated source file
management. The window has several views to display the sources using different methods.
Vivado IDE 源窗口（如下图所示）提供自动源文件管理功能。该窗口有多个视图，可使用不同方法显示源文件。
When you open or modify a project, the Sources window updates the status of the project
sources. A quick compilation of the design source files is performed and the sources appear in
the Compile Order view of the Sources window in the order they will be compiled by the
downstream tools. 打开或修改项目时，"源 "窗口会更新项目源的状态。对设计源文件进行快速编译后，源文件将显示在源窗口的编译顺序视图中，并按照下游工具的编译顺序显示。
Any potential issues with the compilation of the RTL hierarchy are shown as well as reported in the Message window. For more information on sources, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
RTL 层次结构编译中的任何潜在问题都会显示出来，并在消息窗口中报告。
有关源的更多信息，请参见以下链接《Vivado 设计套件用户指南》

TIP: If you explicitly set a module as the top module, the module is retained and passed to synthesis.
However, if you do not explicitly set a top module, the Vivado tools select the best possible top module
from the available source files in the project. If a file includes syntax errors and does not elaborate, this file is not selected as the top module by the Vivado tools.提示：如果显式地将某个模块设置为顶层模块，该模块将被保留并传递给综合。但是，如果不明确设置顶层模块，Vivado 工具会从项目中的可用源文件中选择最佳顶层模块。从项目中的可用源文件中选择最佳的顶层模块。如果文件包含语法错误且未详细说明，则 Vivado 工具不会将该文件选为顶层模块。

Constraints and simulation sources are organized into sets. You can use constraint sets to
experiment with and manage constraints.
You can launch different simulation sessions using different simulation source sets. You can add, remove, disable, or update any of the sources.
约束条件和仿真源被组织成集合。您可以使用约束集实验和管理约束条件。您可以使用不同的仿真源集启动不同的仿真会话。您可以添加、移除、禁用或更新任何仿真源。
For more information on constraints, see the Vivado Design Suite User Guide: Using Constraints
(UG903). For more information on simulation, see the Vivado Design Suite User Guide: Logic
Simulation (UG900).有关有关约束的更多信息，请参阅《Vivado 设计套件用户指南》： 使用约束(UG903)。有关仿真的更多信息，请参见《Vivado 设计套件用户指南》： 逻辑仿真 (UG900)。

RTL Development
The Vivado IDE includes helpful features to assist with RTL development:
Vivado IDE 包含帮助 RTL 开发的有用功能：
• Integrated Vivado IDE Text Editor to create or modify source files

• 集成 Vivado IDE 文本编辑器，用于创建或修改源文件
  • Automatic syntax and language construct checking across multiple source files
• 跨多个源文件的自动语法和语言结构检查
  • Language templates for copying recommended example logic constructs
• 用于复制推荐示例逻辑结构的语言模板
  • Find in Files feature for searching template libraries using a variety of search criteria
• 在文件中查找功能可使用各种搜索条件搜索模板库
  • RTL elaboration and interactive analysis
  • RTL design rule checks
  • RTL constraints assignment and I/O planning
• RTL 详细阐述和交互式分析
• RTL 设计规则检查
• RTL 约束分配和 I/O 规划

RTL Elaboration and Analysis RTL 阐述和分析

When you open an elaborated RTL design, the Vivado IDE compiles the RTL source files and
loads the RTL netlist for interactive analysis. You can check RTL structure, syntax, and logic
definitions. Analysis and reporting capabilities include:
打开精心设计的 RTL 设计时，Vivado IDE 会编译 RTL 源文件，并加载 RTL 网表进行交互式分析。
您可以检查 RTL 结构、语法和逻辑定义。分析和报告功能包括
• RTL compilation validation and syntax checking- RTL 编译验证和语法检查
• Run checks to ensure your RTL is compliant with the UltraFast Methodology rules

• 运行检查以确保您的 RTL 符合 UltraFast 方法规则
  • Netlist and schematic exploration- 网表和原理图探索
  • Design rule checks- 设计规则检查
  • Early I/O pin planning using an RTL port list- 使用 RTL 端口列表进行早期 I/O 引脚规划
  • Ability to select an object in one view and cross probe to the object in other views, including
  instantiations and logic definitions within the RTL source files
• 在一个视图中选择对象，并在其他视图中交叉探测该对象，包括RTL 源文件中的实例和逻辑定义。

For more information on RTL development and analysis features, see the Vivado Design Suite User
Guide: System-Level Design Entry (UG895). For more information on RTL-based I/O planning, see
the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).有关 RTL 开发和分析功能的更多信息，请参阅《Vivado 设计套件用户指南》。指南： 系统级设计输入 (UG895)。有关基于 RTL 的 I/O 规划的更多信息，请参见《Vivado 设计套件用户指南》： I/O 和时钟规划 (UG899)。

Timing Constraint Development and Verification时序约束开发与验证

The Vivado IDE provides a Timing Constraints wizard to walk you through the process of creating
and validating timing constraints for the design.
The wizard identifies clocks and logic constructs in the design and provides an interface to enter and validate the timing constraints in the design.
It is only available in synthesized and implemented designs, because the in-memory design must be clock aware post-synthesis. For more information, see the Vivado Design Suite User Guide:
Using Constraints (UG903).
Vivado IDE 提供了时序约束向导，可指导您完成创建和验证设计时序约束的过程。
该向导可识别设计中的时钟和逻辑结构，并提供输入和验证时序约束的界面。

**它只能在综合和实现的设计中使用，因为内存设计必须在综合后时钟感知。**有关详细信息，请参阅《Vivado 设计套件用户指南》：使用约束 (UG903)。

TIP:
The Vivado Design Suite only supports Synopsys design constraints (SDC) and Xilinx design
constraints (XDC).
It does not support AMD user constraints files (UCF) used with the ISE Design Suite nor does it directly support Synplicity design constraints.
For information on migrating from UCF format to XDC format, see the Migrating UCF Constraints to XDC chapter in the ISE to Vivado Design Suite Migration Guide (UG911).
提示：
Vivado 设计套件仅支持 Synopsys 设计约束 (SDC) 和 Xilinx 设计约束 (XDC)。
它不支持 ISE 设计套件使用的 AMD 用户约束文件 (UCF)，也不直接支持 Synplicity 设计约束。
有关从 UCF 格式迁移到 XDC 格式的信息，请参阅《ISE 到 Vivado 设计套件迁移指南》（UG911）中的 "将 UCF 约束迁移到 XDC "一章。迁移指南 (UG911) 中的将 UCF 约束迁移到 XDC 一章。

5、Working with IP（使用IP）

The Vivado Design Suite provides an IP-centric design flow that lets you configure, implement,
verify, and integrate IP modules to your design from various design sources.
The tool also provides an extensible IP catalog that includes AMD LogiCORE™ IP that can be configured and verified as a standalone module or within the context of a system-level design.
For more information, see the Vivado Design Suite User Guide: Designing with IP (UG896).
Vivado 设计套件提供了以 IP 为中心的设计流程，让您可以配置、实现、验证和集成 IP 模块到您的设计中、验证 IP 模块并将其集成到来自各种设计源的设计中。
该工具还提供了一个可扩展的 IP 目录，其中包括 AMD LogiCORE™ IP，该 IP 可作为独立模块进行配置和验证，也可在层级模块中进行配置和验证。可作为独立模块或在系统级设计中进行配置和验证。
有关更多信息，请参阅《Vivado 设计套件用户指南》： 使用 IP 进行设计 (UG896)。

You can also package custom IP using the IP-XACT protocol and make it available through the
Vivado IP catalog. AMD IP uses the AMBA® AXI4 interconnect standard to enable faster system-
level integration. Existing IP can be added to a design as either RTL source or a netlist.
您还可以使用 IP-XACT 协议打包自定义 IP，并通过Vivado IP 目录提供。AMD IP 采用 AMBA® AXI4 互连标准，以实现更快的系统级集成。现有 IP 可作为 RTL 源或网表添加到设计中。

The available methods to work with IP in a design are as follows:
在设计中使用 IP 的可用方法如下：
• Use the managed IP flow to customize IP and generate output products, including a
synthesized design checkpoint (DCP) to preserve the customization for use in the current and
future releases. For more information, see the Vivado Design Suite User Guide: Design Flows
Overview (UG892).
- 使用托管 IP 流程定制 IP 并生成输出产品，包括一个综合设计检查点 (DCP)，以保留定制内容，供当前和未来版本使用。有关详细信息，请参阅《Vivado 设计套件用户指南》： 设计流程概述 (UG892)。**
• Use IP in either Project or Non-Project modes by importing or reading the created Xilinx
core instance (XCI) file. This is the recommended method for large projects with many team
members.- 通过导入或读取已创建的 Xilinx 内核实例（XCI）文件，在项目或非项目模式下使用 IP。这是有许多团队成员的大型项目的推荐方法。
• Access the IP catalog from a project to customize and add IP to a design. Store the IP files
either local to the project, or save them externally from the project. This is the recommended
method for small team projects.- 从项目中访问 IP 目录，为设计定制和添加 IP。存储 IP 文件
或从项目外部保存。这种方法适用于小型团队项目。**

Configuring IP

The Vivado IP catalog (shown in the following figure) lets you browse the available IP for the
target device in the current project. The catalog shows version and licensing information about
each IP and provides the applicable data sheet.Vivado IP 目录（如下图所示）可让您浏览当前项目中目标器件的可用 IP。当前项目中目标器件的可用 IP。目录显示每个 IP 的版本和许可信息并提供适用的数据表。

The Vivado IP catalog displays either Included or Purchase under the License column in the IP
catalog. The following definitions apply to IP offered by AMD:
Vivado IP 目录中的 IP 许可证列下显示 "包含 "或 “购买”。以下定义适用于 AMD 提供的 IP：
• Included: The AMD End User License Agreement includes AMD LogiCORE™ IP cores that are
licensed within the AMD Vivado Design Suite software tools at no additional charge.

• 包含： AMD 最终用户许可协议包括 AMD LogiCORE™ IP 核，这些 IP 核在 AMD Vivado 设计软件中获得许可。在 AMD Vivado Design Suite 软件工具中授权使用的 AMD LogiCORE™ IP 核，不收取额外费用。
  • Purchase: The Core License Agreement applies to fee-based AMD LogiCORE IP, and the Core
  Evaluation License Agreement applies to the evaluation of fee-based AMD IP.- 购买： 核心许可协议适用于收费的 AMD LogiCORE IP，核心评估许可协议适用于收费的 AMD IP 评估。
  

This license status information is available for IP cores used in a project using Report IP Status by
selecting Reports → Report IP Status. For additional information on how to obtain IP licenses, see
the Xilinx IP Licensing page.项目中使用的 IP 核可通过报告 IP 状态获得此许可状态信息，方法是
选择报告 → 报告 IP 状态。有关如何获取 IP 许可证的更多信息，请参阅Xilinx IP 许可页面。
AMD and its partners provide additional IP cores that are not shipped as part of the default
Vivado IP Catalog. For more information on the available IP, see the Intellectual Property page on
the AMD website.AMD 及其合作伙伴提供了额外的 IP 内核，这些 IP 内核不作为默认的Vivado IP 目录的一部分。有关可用 IP 的更多信息，请参阅 AMD 网站上的知识产权页面。
You can double-click any IP to launch the Configuration wizard to instantiate an IP into your
design.
After configuring the IP, a Xilinx core instance (.xci) file is created. This file contains all
the customization options for the IP.
From this file the tool can generate all output products for the IP.
These output products consist of HDL for synthesis and simulation, constraints, possibly a
test bench, C modules, example designs, etc. The tool creates these files based upon the
customization options used.
您可以双击任何 IP 来启动配置向导，将 IP 实例化到您的设计中。
设计中。
配置 IP 后，会创建一个 Xilinx 内核实例（.xci）文件。该文件包含 IP 的所有IP 的自定义选项。
通过该文件，工具可为 IP 生成所有输出产品。
这些输出产品包括用于综合和仿真的 HDL、约束、可能的测试台、C 模块、示例设计等。工具会根据
自定义选项来创建这些文件。

Generating IP Output Products 生成 IP 输出产品

IP output products are created to enable synthesis, simulation, and implementation tools to use a
specific configuration of the IP.
While generating output products, a directory structure is set up to store the various output products associated with the IP.
The folders and files are fairly self-explanatory and should be left intact. The Vivado Design Suite generates the following output products:
创建 IP 输出产品是为了使综合、仿真和实现工具能够使用 IP 的特定配置。
在生成输出产品时，会建立一个目录结构，以存储与 IP 相关的各种输出产品。
文件夹和文件的作用不言而喻，应保持不变。Vivado 设计套件会生成以下输出产品：
• Instantiation template- 实例模板
• RTL source files and XDC constraints- RTL 源文件和 XDC 约束
• Synthesized design checkpoint (default)- 合成设计检查点（默认）
• Third-party simulation sources- 第三方仿真源
• Third-party synthesis sources- 第三方综合源
• Example design (for applicable IP)- 示例设计（适用于 IP）
• Test bench (for applicable IP)- 测试台（适用于 IP）
• C Model (for applicable IP)- C 模型（适用于 IP）

TIP: In Project Mode, missing output products are automatically generated during synthesis, including a
synthesized design checkpoint (DCP) file for the out-of-context flow. In Non-Project Mode, the output
products must be manually generated prior to global synthesis.提示：在项目模式下，合成过程中会自动生成缺失的输出产品，包括一个综合设计检查点 (DCP) 文件。在非项目模式下产品必须在全局综合之前手动生成。

For each IP customized in your design, you should generate all available output products,
including a synthesized design checkpoint. 对于设计中定制的每个 IP，都应生成所有可用的输出产品、包括综合设计检查点。
Doing so provides you with a complete representation of the IP that can be archived or placed in revision control. 这样做可以提供完整的 IP 表示，并将其存档或置于修订控制中。
If future Vivado Design Suite versions do not include that IP, or if the IP has changed in undesirable ways (such as interface changes),you have all the output products required to simulate, and to use for synthesis and implementation with future Vivado Design Suite releases.
如果未来的 Vivado 设计套件版本不包含该 IP，或者该 IP 发生了不良变化（如接口变化）、您将拥有仿真所需的所有输出产品，并在未来的 Vivado Design Suite 版本中用于综合和实现所需的所有输出产品。

Using IP Core Containers使用 IP 核容器

The optional Core Container feature helps simplify working with revision control systems by
providing a single file representation of an IP.
By enabling this option, you can store IP configuration files (XCI) and output products in a single, binary IP core container file (XCIX) rather than a loose directory structure. The XCIX file is similar to the XCI file and works in a similar way in the tool.
For more information on using IP core containers, see the Vivado Design Suite User Guide: Designing with IP (UG896).
可选的核心容器功能通过提供单一文件表示 IP，有助于简化修订控制系统的工作。
启用该选项后，可将 IP配置文件 (XCI) 和输出产品存储在一个二进制 IP 内核容器文件 (XCIX) 中，而不是一个松散的目录结构中。
XCIX 文件与 XCI 文件类似，在工具中的工作方式也类似。
有关使用 IP 核容器的更多信息，请参阅《Vivado 设计套件用户指南：IP 设计》 (UG896)。

Out-of-Context Design Flow “脱离上下文联系”的设计流程

By default, the Vivado Design Suite uses an out-of-context (OOC) design flow to synthesize IP
from the IP catalog, and block designs from the Vivado IP integrator. 默认情况下，Vivado 设计套件使用上下文外 (OOC) 设计流程来综合 IP 目录中的 IP和来自 Vivado IP 集成器的块设计。
This OOC flow lets you synthesize, implement, and analyze design modules in a hierarchical design, IP cores, or block designs, independent of the top-level design. The OOC flow reduces design cycle time, and eliminates design iterations, letting you preserve and reuse synthesis results.该 OOC 流程可让您综合、实现和分析分层设计、IP 核或块设计中的设计模块，独立于顶层设计。OOC 流程可缩短设计周期，并消除了设计迭代，让您可以保留并重复使用综合结果。

IP cores that are added to a design from the Vivado IP catalog default to use the out-of-context
flow. For more information, see the Vivado Design Suite User Guide: Designing with IP (UG896).
Block designs created in the Vivado IP integrator also default to the OOC flow when generating
output products. For more information, see this link in the Vivado Design Suite User Guide:
Designing IP Subsystems Using IP Integrator (UG994).从 Vivado IP 目录添加到设计中的 IP 核默认使用脱离上下文的流程。有关详细信息，请参阅《Vivado Design Suite 用户指南》： 使用 IP 进行设计 (UG896)。
生成输出产品时，在 Vivado IP 集成器中创建的块设计也默认使用 OOC 流程。有关详细信息，请参见《Vivado Design Suite 用户指南》中的此链接：使用 IP 集成器设计 IP 子系统 (UG994)。

The Vivado Design Suite also supports global synthesis and implementation of a design, in which
all modules, block designs, and IP cores, are synthesized as part of the integrated top-level
design. Vivado 设计套件还支持设计的全局综合和实现。在这种情况下，所有模块、块设计和 IP 内核都将作为集成顶层设计的一部分进行综合。
You can mark specific modules or IP for out-of-context synthesis, and other modules for
inclusion in the global synthesis of the top-level design. 您可以将特定模块或 IP 标记为上下文外综合，将其他模块纳入顶层设计的全局综合中。

In the case of a block design from Vivado IP integrator, the entire block design can be specified for OOC synthesis, or you can specify OOC synthesis for each individual IP, or per IP used in the block design.

When run in global mode,Vivado synthesis has full visibility of design constraints. When run in OOC mode, estimated constraints are used during synthesis.

对于来自 Vivado IP 集成器的块设计，可以为 OOC 综合指定整个块设计，也可以为每个单个 IP 指定 OOC或块设计中使用的每个 IP 指定 OOC 综合。
在全局模式下运行时、Vivado 综合对设计约束具有完全可见性。在 OOC 模式下运行时，在综合过程中会使用估计的约束。

The Vivado synthesis tool also provides a cache to preserve OOC synthesis results for reuse in
other designs that use the same IP customization. This can significantly speed synthesis of large
complex designs.Vivado 综合工具还提供了一个缓存，用于保存 OOC 综合结果，以便在使用相同 IP 定制的其他设计中重复使用。这可以大大加快大型复杂设计的综合速度。

A design checkpoint (DCP) is created for OOC IP or modules, which contains the synthesized
netlist and design constraints. 为 OOC IP 或模块创建设计检查点 (DCP)，其中包含合成网表和设计约束。
OOC modules are seen as black boxes in the top-level design until the synthesized design is open and all the elements are assembled. OOC 模块在顶层设计中被视为黑盒，直到综合设计打开和所有元素组装完成。
Before the top-level synthesized design is opened, resource utilization, and analysis of the top-level design might not include netlist or resource information from the OOC modules, or black boxes, and so will not provide a complete view of the design.
在顶层综合设计打开之前，顶层设计的资源利用和分析可能不包括来自 OOC 模块或黑盒的网表或资源信息，因此无法提供完整的设计视图。

IMPORTANT! To obtain more accurate reports, you should open and analyze the top-level synthesized design, which will include all the integrated OOC modules.重要！为获得更准确的报告，您应打开并分析顶层综合设计。该设计将包括所有集成的 OOC 模块。

The OOC flow is supported in Vivado synthesis, implementation, and analysis. For more
information refer to the Vivado Design Suite User Guide: Synthesis (UG901). Vivado 综合、实现和分析均支持 OOC 流程。更多信息请参阅《Vivado 设计套件用户指南》： 综合 (UG901)。

OOC synthesis can also be used to define a hierarchical design methodology and a team design approach as defined in the Vivado Design Suite User Guide: Hierarchical Design (UG905).
OOC 综合法也可用于定义分层设计方法和团队设计方法，如《Vivado 设计套件用户指南》中所定义的分层设计方法和团队设计方法： 分层设计 (UG905)。

IP Constraints IP 约束

Many IP cores contain XDC constraint files that are used during Vivado synthesis and
implementation. These constraints are applied automatically in both Project Mode and Non-
Project Mode if the IP is customized from the Vivado IP catalog.
许多 IP 核都包含 XDC 约束文件，可在 Vivado 综合和实现过程中使用。如果从 Vivado IP 目录中定制了 IP，这些约束会自动应用于项目模式和非项目模式中自动应用。

Many IP cores reference their input clocks in these XDC files. These clocks can come either from
the user through the top level design, or from other IP cores in the design. By default, the Vivado
tools process any IP clock creation and any user-defined top-level clock creation early. This
process makes these clocks available to the IP cores that require them. Refer to Vivado Design
Suite User Guide: Designing with IP (UG896) for more information.许多 IP 内核会在这些 XDC 文件中引用其输入时钟。这些时钟可以来自这些时钟可以来自用户的顶层设计，也可以来自设计中的其他 IP 核。默认情况下，Vivado工具会提前处理任何 IP 时钟创建和任何用户定义的顶层时钟创建。该流程会将这些时钟提供给需要它们的 IP 核。请参阅《Vivado 设计套件用户指南：使用 IP 进行设计》（UG896）。

Validating the IP 验证IP

You can verify Vivado IP by synthesizing the IP and using behavioral or structural logic
simulation, and by implementing the IP module to validate timing, power, and resource
utilization.
Typically, a small example design is used to validate the standalone IP.
You can also validate the IP within the context of the top-level design project. Because the IP creates
synthesized design checkpoints, this bottom-up verification strategy works well either standalone or within a project.
您可以通过综合 Vivado IP 并使用行为或结构逻辑仿真来验证 Vivado IP，也可以通过实现 IP 模块来验证时序、功耗和资源利用率。
通常情况下，使用一个小型示例设计来验证独立 IP。
您还可以在顶层设计项目中验证 IP。因为 IP 会创建综合设计检查点，因此这种自下而上的验证策略无论是独立验证还是在项目中验证都很有效。

Many of the AMD IP delivered in the Vivado IP catalog have an example design. You can
determine if an IP comes with an example design by selecting the IP from the IP Sources area of
the Manage IP or RTL project and see if the Open IP Example Design is selectable, as shown in
the following figure. This can also be done using Tcl by examining the SUPPORTED_TARGETS
property of the IP.
Vivado IP 目录中提供的许多 AMD IP 都有一个示例设计。您可以从管理 IP 或 RTL 项目的 IP 源区域选择 IP，查看是否可选择 “打开 IP 示例设计”（Open IP Example Design）。即可确定 IP 是否附带示例设计，如下图所示。也可以使用 Tcl 检查 IP 的 SUPPORTED_TARGETS属性。

Use the Open IP Example Design right-click menu command for a selected IP to create an
example design to validate the standalone IP within the context of the example design project.
For more details on working with example designs and IP output products, refer to the Vivado
Design Suite User Guide: Designing with IP (UG896).
对选定的 IP 使用 "打开 IP 示例设计 "右键单击菜单命令，可在示例设计项目的背景中创建一个
示例设计，以在示例设计项目的背景中验证独立 IP。有关使用示例设计和 IP 输出产品的更多详情，请参阅《Vivado设计套件用户指南》： 使用 IP 进行设计 (UG896)。

Some IP deliver test benches with the example design, which you can use to validate the
customized IP functionality.
You can run behavioral, post synthesis, or post-implementation simulations. You can run either functional or timing simulations. In order to perform timing/functional simulations you will need to synthesize/implement the example design.
For specific information on simulating an IP, refer to the product guide for the IP. For more detail on
simulation, refer to the Vivado Design Suite User Guide: Logic Simulation (UG900).
有些 IP 提供了带有示例设计的测试平台，您可以用它来验证定制的 IP 功能。
您可以运行行为仿真、综合后仿真或实现后仿真。您可以运行功能仿真或时序仿真。要执行时序/
功能仿真，您需要综合/实现示例设计。
有关模拟 IP 的具体信息，请参阅 IP 的产品指南。有关仿真的更多详情请参阅《Vivado 设计套件用户指南》： 逻辑仿真 (UG900)。

Using Memory IP

Additional I/O pin planning steps are required when using AMD memory IP.
After the IP is customized, you then assign the top-level I/O ports to physical package pins in either the
elaborated or synthesized design in the Vivado IDE.
使用 AMD 存储器 IP 时，需要额外的 I/O 引脚规划步骤。
IP 定制后，在 Vivado IDE 中将顶层 I/O 端口分配给详细设计或综合设计中的物理封装引脚。

All of the ports associated with each memory IP are grouped together into an I/O Port Interface
for easier identification and assignment. A Memory Bank/Byte Planner is provided to assist you
with assigning Memory I/O pin groups to Byte lanes on the physical device pins.
与每个内存 IP 相关的所有端口都归入一个 I/O 端口接口，以便于识别和分配。
内存库/字节规划器可帮助您将存储器 I/O 引脚组分配到物理设备引脚的字节通道上

For more information, see this link in the Vivado Design Suite User Guide: I/O and Clock Planning
(UG899).

If you have memory IP in your design, see the following resources:
如果您的设计中有存储器 IP，请参阅以下资源：
• For details on simulation, see the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP
Product Guide (PG150).

• 有关仿真的详细信息，请参阅《基于 UltraScale 架构的 FPGA 存储器 IP LogiCORE IP
• 产品指南 (PG150)。
  • For an example of simulating memory IP with a MicroBlaze™ processor design, see the
  Reference System: Kintex-7 MicroBlaze System Simulation Using IP Integrator (XAPP1180).
• 有关使用 MicroBlaze™ 处理器设计模拟内存 IP 的示例，参考系统： 使用 IP Integrator 进行 Kintex-7 MicroBlaze 系统仿真 (XAPP1180)。

Packaging Custom IP and IP Subsystems 封装定制 IP 和 IP 子系统

The Vivado Design Suite lets you package custom IP or block designs into IP to list in the Vivado
IP catalog for use in designs or in the Vivado IP integrator.
You can package IP from a variety of sources, such as from a collection of RTL source files, a Vivado IP integrator block design, or an entire Vivado Design Suite project.
通过 Vivado 设计套件，您可以将自定义 IP 或块设计打包成 IP，并将其列入 Vivado IP 目录中，以便在设计中或 Vivado IP 集成器中使用。
您可以将各种源封装成IP，如 RTL 源文件集合、Vivado IP 集成器块设计或整个 Vivado Design Suite 项目。

The location of the packaged IP can be added to the IP Repository section of the Settings dialog
box which can be accessed through the Tools → Settings menu in the Vivado IDE.
After a repository of one or more IP has been added, the IP core(s) from the repository will be shown in
the IP catalog.
打包 IP 的位置可添加到 "设置 "对话框的 "IP 资源库 "部分。该对话框可通过 Vivado IDE 中的 "工具"→"设置 "菜单访问。
在添加了一个或多个 IP 存储库后，存储库中的 IP 核将显示在IP 目录中。

TIP: Before packaging your IP HDL, ensure its correctness by simulating and synthesizing to validate the
design.
提示：在打包 IP HDL 之前，通过仿真和综合验证设计，确保其正确性。

There are multiple ways to configure the IP and make it available for use within the Vivado IP
catalog and IP integrator.
For example, the Create and Package IP wizard takes you step-by-step through IP packaging and lets you package IP from a project, a block design, or a specified directory.
You can also create and package a new template AXI4 peripheral for use in embedded processor designs.
有多种方法可配置 IP 并使其可在 Vivado IP目录和 IP 集成器中使用。
例如，"创建和打包 IP 向导 "可让您逐步完成 IP 打包，并可让您从项目、块设计或指定的设计中打包 IP。
您还可以创建和封装一个新的 AXI4 外围设备模板，用于嵌入式处理器设计中使用。

IMPORTANT! Ensure that the desired list of supported device families is defined properly while creating
the custom IP definition. This is especially important if you want your IP to be used with multiple device
families.
重要！确保在创建自定义 IP 定义时正确定义了所需的支持设备系列列表。如果您希望将 IP 用于多个设备系列，这一点尤为重要。

For more information, see the Vivado Design Suite User Guide: Creating and Packaging Custom IP
(UG1118) and Vivado Design Suite Tutorial: Creating, Packaging Custom IP (UG1119).
有关详细信息，请参阅《Vivado 设计套件用户指南》： 创建和封装自定义 IP(UG1118) 和 Vivado Design Suite 教程： 创建和封装自定义 IP (UG1119)。

Upgrading IP 升级IP

With each release of the Vivado Design Suite, new IP versions are introduced. It is recommended
that you upgrade the IP used in your designs at each new release.
However, you can also use the older version as a static IP that is already configured and synthesized to avoid introducing any unnecessary changes into your design.
To use the static version of an existing IP, all of the output products must have been previously generated for the IP, and no changes to those generated output files will be possible.
Vivado 设计套件的每个版本都会推出新的 IP 版本。建议您在每次发布新版本时升级设计中使用的 IP。
不过，您也可以将旧版本作为已配置和综合的静态 IP，以避免在设计中引入任何不必要的更改。
要使用现有 IP 的静态版本，所有输出产品都必须是先前为该 IP 生成的，并且不能更改这些生成的输出文件。

For more information refer to this link in the Vivado Design Suite User Guide: Designing with IP (UG896).

To report on the current status of the IP in a design, you can use the report_ip_status Tcl
command. See Vivado Design Suite Tcl Command Reference Guide (UG835) for more information.
要报告设计中 IP 的当前状态，可以使用 report_ip_status Tcl 命令来报告设计中 IP 的当前状态。有关详细信息，请参阅《Vivado Design Suite Tcl 命令参考指南》(UG835)。

If changes are needed, you can selectively upgrade the IP in the design to the latest version. A
change log for each IP details the changes made and lists any design updates that are required.
如需要更改，可以选择性地将设计中的 IP 升级到最新版本。每个 IP 的更改日志会详细说明所做的更改，并列出所需的任何设计更新。

For example, top-level port changes are occasionally made in newer IP versions, so some design
modification might be required. 例如，更新的 IP 版本偶尔会对顶层端口进行更改，因此可能需要对设计进行一些修改。If the IP version has changed in the latest release, the version
used in the design becomes locked and must be used as a static IP with the available output
products, or must be updated to support the current release. 如果 IP 版本在最新版本中发生了变化，那么设计中使用的版本在设计中使用的版本就会被锁定，必须作为静态 IP 与可用的输出产品一起使用，或者必须更新以支持最新的 IP 版本。
Locked IP are reported as locked,and appear with a lock symbol in the Sources window of the Vivado IDE.锁定的 IP 会被报告为已锁定、并在 Vivado IDE 的 "来源 "窗口中显示锁定符号。

6、Creating IP Subsystems with IP Integrator（使用 IP 集成器创建 IP 子系统）

The Vivado IP integrator enables the creation of Block Designs (.bd), or IP subsystems with multiple IP stitched together using the AXI4 interconnect protocol.
The IP integrator lets you quickly connect IP cores to create domain specific subsystems and designs, including embedded processor-based designs using AMD Zynq™ UltraScale+™ MPSoC, AMD Zynq™ 7000 SoC, and MicroBlaze™ processors.
It can instantiate High-Level Synthesis modules from Vivado HLS, DSP modules from System Generator, and custom user-defined IP as described in Packaging Custom IP and IP Subsystems.
Vivado IP 集成器可创建块设计（.bd），或使用 AXI4 互连协议将多个 IP 拼接在一起的 IP 子系统。
通过 IP 集成器，可让您快速连接 IP 内核，创建特定领域的子系统和设计，包括使用 AMD ZD 处理器的嵌入式基于处理器的设计，包括使用 AMD Zynq™ UltraScale+™ MPSoC、AMD Zynq™ 7000 SoC 和MicroBlaze™ 处理器。

它可以实例化 Vivado HLS 的高层次综合模块、System Generator 的 DSP
模块和自定义用户定义 IP（如打包自定义 IP 和 IP 子系统中所述）。

Using Vivado IP integrator you can drag and drop IP onto the design canvas, connect AXI interfaces with one wire, and place ports and interface ports to connect the IP subsystem to the top-level design.
使用 Vivado IP integrator，您可以将 IP 拖放到设计画布上，用一根线连接 AXI 接口，并放置端口和接口端口，将 IP 子系统连接到顶层设计。
These IP block designs can also be packaged as sources (.bd) and reused in other designs.
这些 IP 块设计还可以打包为源 (.bd) 并在其他设计中重复使用。
For more information, see the Vivado Design Suite User Guide: Designing IP
Subsystems Using IP Integrator (UG994) or MicroBlaze Processor Embedded Design User Guide(UG1579).
有关详细信息，请参阅《Vivado 设计套件用户指南： 设计 IP子系统》（UG994）或《MicroBlaze 处理器嵌入式设计用户指南》（UG1579）。

Related Information
Packaging Custom IP and IP Subsystems

Building IP Subsystems
The interactive block design capabilities of the Vivado IP integrator make the job of configuring and assembling groups of IP easy.Vivado IP 集成器的交互式模块设计功能使 IP 组的配置和组装工作变得简单。

TIP: If you prefer to work with a Tcl script, it is suggested to create the block design interactively using the Vivado IDE and then capture and edit the script as needed to recreate the block design. The IP integrator can create a Tcl script to re-create the current block design in memory.
提示：如果您喜欢使用 Tcl 脚本，建议使用 Vivado IDE 以交互方式创建模块设计，然后根据需要捕获和编辑脚本以重新创建模块设计。IP 集成器可以创建 Tcl 脚本，在内存中重新创建当前的模块设计。

Block Design Containers

Block design containers allow a block diagram to reference a secondary block diagram. This enables a design to be partitioned into several block diagrams. Block design containers also support several instances of child block diagrams in a parent block diagram. In this manner, a logic can be replicated even if each instance has different parametrization. For more information on block design containers, see Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994).
块设计容器允许一个方框图引用另一个方框图。这样就可以将一个设计分割成多个框图。块设计容器还支持父块图中的多个子块图实例。这样，即使每个实例具有不同的参数化，也可以复制逻辑。有关块设计容器的更多信息，请参阅《Vivado 设计套件用户指南： 使用 IP Integrator 设计 IP 子系统 (UG994)》

Referencing RTL Modules in Block Designs在块设计中引用 RTL 模块

The Module Reference feature of the Vivado IP integrator lets you quickly add a module or entity definition from a Verilog or VHDL source file directly into your block design. Vivado IP 集成器的模块参考功能可让您快速将 Verilog 或 VHDL 源文件中的模块或实体定义直接添加到块设计中。

This provides a means of quickly adding RTL modules without having to go through the process of packaging the RTL as an IP to be added through the Vivado IP catalog. 这提供了一种快速添加 RTL 模块的方法，而无需经过将 RTL 封装为 IP 的过程。

The Module Reference flow is quick, but does not offer the benefits of the working through the IP catalog. Both flows have the benefits and associated limitations. Refer to this link in Vivado Design Suite User Guide: Designing IP
Subsystems Using IP Integrator (UG994) for more information.
**模块参考流程虽然快速，但但不具备通过 IP 目录工作的优势。两种流程都有优点和相关限制。**请参阅《Vivado 设计套件用户指南： 设计 IP
子系统》（UG994）中的链接了解更多信息。

Designer Assistance

To expedite the creation of a subsystem or a design, the IP integrator offers Block Automation and Connection Automation. 为加快子系统或设计的创建速度，IP 集成商提供了块自动化和连接自动化功能。
The Block Automation feature can be used to configure a basic processor-based design and some complex IP subsystems, while the Connection Automation feature can be used to automatically make repetitive connections to different pins or ports of the design. 块自动化功能可用于配置基本的基于处理器的设计和一些复杂的 IP 子系统，而连接自动功能则可用于自动重复连接设计的不同引脚或端口。
IP integrator also supports all the AMD evaluation boards in the Platform Board Flow, as described below in Using the Platform Board Flow.IP 集成器还支持平台电路板流程中的所有 AMD 评估电路板，如下文 "使用平台电路板流程 "中所述。
This lets the Connection Automation feature connect the I/O ports of the design to components on the target board. Designer assistance also helps with defining and connecting clocks and resets. Using Designer Assistance not only expedites the design process but also helps prevent unintended design errors。这使得连接自动化功能将设计的 I/O 端口连接到目标板上的组件。设计人员辅助功能还帮助定义和连接时钟和复位。使用设计器辅助不仅可以还有助于防止意外设计错误。

Related Information
Using the Platform Board Flow

Using the Platform Board Flow使用平台电路板流程

The Vivado Design Suite is board aware and can automatically derive I/O constraints and IP configuration data from included board files.
Through the board files, the Vivado Design Suite knows the various components present on the target boards and can customize and configure an IP to be connected to a particular board component. Several 7 series, AMD Zynq™ 7000 SoC,and AMD UltraScale™ device boards are currently supported. You can download support files for partner-developed boards from the partner websites or from the AMD Vivado Store.
Vivado 设计套件具有电路板感知功能，可从包含的电路板文件中自动导出 I/O 约束和 IP 配置数据。
通过电路板文件，Vivado 设计套件可了解目标电路板上的各种组件，并可定制和配置 IP，使其连接到特定的电路板组件。多个 7 系列、AMD Zynq™ 7000 SoC、和 AMD UltraScale™ 器件电路板。您可以从合作伙伴网站或 AMD Vivado Store 下载合作伙伴开发板的支持文件。

The IP integrator shows all the component interfaces on the target board in a separate tab called the Board tab. You can use this tab to connect to the desired components through the Designer Assistance feature. All the I/O constraints are automatically generated as a part of using this feature.
IP integrator 会在一个名为 “电路板”（Board）选项卡的单独选项卡中显示目标电路板上的所有元件接口。您可以使用该选项卡，通过设计器辅助功能连接到所需的元件。作为使用该功能的一部分，所有 I/O 约束都会自动生成。
You can also generate board files for custom boards and add the repository that contains the board file to a project. For more information on generating a custom board file, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
您还可以为自定义电路板生成电路板文件，并将包含电路板文件的资源库添加到项目中。有关生成自定义电路板文件的更多信息，请参阅《Vivado Design Suite 用户指南》中的此链接： 系统级设计输入 (UG895) 中的链接。

Validating IP Subsystems 验证IP子系统

IP integrator runs basic design rule checks in real time as the design is being assembled.
However, there is still a potential for design errors, such as the frequency on a clock pin can be set incorrectly. The tool can catch these types of errors by running a more thorough design validation. You can run design validation by selecting Tools → Validate Design or through the Tcl command validate_bd_design.
IP 集成器在组装设计时实时运行基本的设计规则检查。
不过，仍有可能出现设计错误，例如时钟引脚的频率可能设置错误。该工具可以通过运行更彻底的设计验证来捕捉这些类型的错误。您可以选择工具 → 验证设计或通过 Tcl 命令 validate_bd_design 运行设计验证。

The Validate Design command applies design rule checks on the block design and reports warnings and/or errors found in the design. You can cross-probe the warnings and/or errors from the Messages window to locate objects in the block diagram.
AMD recommends validating a block design to catch errors that would otherwise be found later in the design flow.
Running design validation also runs Parameter Propagation on the block design.
验证设计 命令对块设计进行设计规则检查，并报告设计中发现的警告和/或错误。您可以从 "信息 "窗口交叉探测警告和/或错误，以查找框图中的对象。AMD 建议对块设计进行验证，以捕捉设计流程中稍后会发现的错误。
运行设计验证也会在块设计上运行参数传播。

Parameter Propagation enables IP integrator to automatically update the parameters associated with a given IP based on its context and its connections in the design.
You can package custom IP with specific parameter propagation rules, and IP integrator applies these rules as the block diagram is generated and validated. See this link in Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for more information.
参数传播功能使 IP integrator 能够根据特定 IP 的上下文及其在设计中的连接自动更新与该 IP 相关的参数。
您可以使用特定的参数传播规则打包自定义 IP，IP integrator 会在生成和验证框图时应用这些规则。请参见 Vivado Design Suite 用户指南中的链接： 使用 IP Integrator 设计 IP 子系统 (UG994) 中的链接了解更多信息。

Generating Block Design Output Products

After the block design or IP subsystem has been created, you can generate the block design
including all source codes, necessary constraints for the IP cores, and the structural netlist of the
block design. You can generate the block design by right-clicking on the block design (in the
Sources window) and selecting Generate Output Products from the pop-up menu. In the Vivado
Design Suite Flow Navigator you can also select IP Integrator → Generate Block Design.
There are two modes of OOC supported for block designs in the Vivado Design Suite: Out of
context per Block design and Out of context per IP. Refer to Out-of-Context Design Flow for
more information.

Related Information
Out-of-Context Design Flow

Integrating the Block Design into a Top-Level Design
将模块设计融入顶层设计

An IP integrator block design can be integrated into a higher-level design or it can be the highest level in the design hierarchy. To integrate the IP integrator design into a higher-level design,instantiate the block design as a module in the higher-level HDL file.
IP 集成块设计可以集成到上一级设计中，也可以是设计层次结构中的最高级别。设计层次结构中的最高级别。要将 IP 集成块设计集成到更高层次的设计中，可采用以下方法在高层 HDL 文件中将模块设计实例化。

You can perform a higher-level instantiation of the block design by selecting the block design in the Vivado IDE Sources window and selecting Create HDL Wrapper.
在 Vivado IDE 源窗口中选择块设计并选择创建 HDL 封装器，即可对块设计执行更高级别的实例化。
This generates a top-level HDL file for the IP integrator sub-system. See this link in the Vivado Design Suite User Guide:
Designing IP Subsystems Using IP Integrator (UG994) for more information.
这会生成一个顶层子系统的顶层 HDL 文件。
请参见《Vivado 设计套件用户指南》中的此链接：使用 IP 集成器设计 IP 子系统 (UG994)，了解更多信息。

7、Logic Simulation 逻辑仿真

The Vivado Design Suite has several logic simulation options for verifying designs or IP. The Vivado simulator, integrated into the Vivado IDE, allows you to simulate the design, add and view signals in the waveform viewer, and examine and debug the design as needed.
Vivado 设计套件有多个逻辑仿真选项，用于验证设计或 IP。集成到 Vivado IDE 中的 Vivado 仿真器可让您对设计进行仿真，在波形查看器中添加和查看信号，并根据需要检查和调试设计。
You can use the Vivado simulator to perform behavioral and structural simulation of designs as well as full timing simulation of implemented designs. 您可以使用 Vivado 仿真器对设计进行行为和结构仿真，以及对已实现的设计进行全时序仿真。
The previous figure shows all the places where Vivado simulation could be used for functional and timing simulation. You can also use third-party simulators by writing Verilog or VHDL netlists, and SDF files from the elaborated, synthesized, or implemented design. 上图显示了 Vivado 仿真可用于功能和时序仿真的所有位置。您还可以通过编写第三方仿真器，编写 Verilog 或 VHDL 网表，并从精心设计、综合或实现的设计中编写 SDF 文件。

The Vivado IDE lets you configure and launch simulators from Mentor Graphics, Synopsys, Cadence, and Aldec. For more information, see this link in the Vivado Design Suite User Guide: Logic Simulation (UG900).
Vivado IDE 可让您配置和启动来自 Mentor Graphics、Synopsys、Cadence 和 Aldec 的仿真器。有关详细信息，请参阅《Vivado 设计套件用户指南》中的链接： 逻辑仿真 (UG900)。

Simulation Flow Overview 仿真流程概述

The following are some key suggestions related to simulating in the Vivado Design Suite. Many of these tips are described in greater detail in the text that follows, or in Vivado Design Suite User Guide: Logic Simulation (UG900).以下是有关在 Vivado Design Suite 中进行仿真的一些关键建议。下文或《Vivado Design Suite 用户指南》将详细介绍其中的许多提示： 逻辑仿真 (UG900)

1. Run behavioral simulation before proceeding with synthesis and implementation. Issues identified early will save time and money.1. 在进行综合和实现之前运行行为仿真。及早发现问题将节省时间和金钱。
2. Infer logic wherever possible. Instantiating primitives adds significant simulation runtime cost.2. 尽可能推导逻辑。实例化基元会增加大量仿真运行时间成本
3. Always set the Simulator Language to Mixed unless you do not have a mixed mode license for your simulator.3. 始终将模拟器语言设置为混合，除非您的模拟器没有混合模式许可证。
4. Turn off the waveform viewer when not in use to improve simulation performance.4. 不使用波形查看器时应将其关闭，以提高仿真性能。
5. In the Vivado simulator, turn off debug during xelab for a performance boost.5. 在 Vivado 仿真器中，关闭 xelab 期间的调试以提高性能。
6. In the Vivado simulator, turn on multi-threading to speed up compile time.6. 在 Vivado 仿真器中，打开多线程以加快编译时间。
7. When using third-party simulators, always target supported versions. For more information,see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).7. 使用第三方仿真器时，请始终使用受支持的版本。有关详细信息，请参阅《Vivado Design Suite 用户指南》： 版本说明、安装和许可 (UG973)。
8. Make sure incremental compile is turned on when using third-party simulators.8. 使用第三方仿真器时，确保已打开增量编译。
9. Use the AMD Tcl command export_simulation to generate batch scripts for selected simulators.9. 使用 AMD Tcl 命令 export_simulation 为选定的仿真器生成批脚本。
10. Generate simulation scripts for individual IP, BDs, and hierarchical modules as well as for the top-level design.10. 为单个 IP、BD 和分层模块以及顶层设计生成仿真脚本。
11. If you are targeting a 7 series device, use UNIFAST libraries to improve simulation performance.11. 如果您的目标是 7 系列器件，请使用 UNIFAST 库来提高仿真性能。

Note: The UNIFAST libraries are not supported for UltraScale device primitives.注意：UltraScale 器件基元不支持 UNIFAST 库。

Compiling Simulation Libraries编译仿真库

Vivado delivers precompiled simulation libraries for use with the Vivado simulator, as well as precompiled libraries for all the static files required by AMD IP. When simulation scripts are created, they reference these precompiled libraries.Vivado 提供用于 Vivado 仿真器的预编译仿真库，以及 AMD IP 所需的所有静态文件的预编译库。创建仿真脚本时，它们会引用这些预编译库。

When using third-party simulators, you must compile AMD simulation libraries prior to running simulation, as explained in the Vivado Design Suite User Guide: Logic Simulation (UG900). This is especially true if your design instantiates VHDL primitives or AMD IP, the majority of which are
in VHDL form. The simulation tool will return “library binding” failures if you do not precompile simulation libraries.使用第三方仿真器时，必须在运行仿真之前编译 AMD 仿真库，具体说明请参见《Vivado 设计套件用户指南》： 逻辑仿真 (UG900) 中的说明。如果您的设计实例化了 VHDL 基元或 AMD IP，则尤其需要这样做。如果不对仿真库进行预编译，仿真工具将返回 "库绑定 "失败。

You can run the compile_simlib Tcl command to compile the AMD simulation libraries for the target simulator. You can also issue this command from the Vivado IDE by selecting Tools → Compile Simulation Libraries.您可以运行 compile_simlib Tcl 命令为目标模拟器编译 AMD 仿真库。您也可以在 Vivado IDE 中选择工具 → 编译仿真库来发布该命令。

IMPORTANT! Simulation libraries are pre-compiled and provided for use with the Vivado simulator.However, you must manually compile the libraries for use with a third-party simulator. Refer to this link in the Vivado Design Suite User Guide: Logic Simulation (UG900) for more information.重要！仿真库已预编译并提供给 Vivado 仿真器使用。但是，您必须手动编译这些库才能与第三方仿真器一起使用。请参阅《Vivado 设计套件用户指南》中的此链接： 有关详细信息，请参阅《Vivado 设计套件用户指南：逻辑仿真》（UG900）中的此链接。

Simulation Time Resolution仿真时间精度

AMD recommends that you run simulations using a resolution of 1 ps. Some AMD primitive components, such as MMCM, require a 1 ps resolution to work properly in either functional or timing simulation.AMD 建议您使用 1 ps 的分辨率运行仿真。某些 AMD 原始元件（如 MMCM）需要 1 ps 的分辨率才能在功能或时序仿真中正常工作。

TIP: Because most of the simulation time is spent in delta cycles, there is no significant simulator performance gain by using coarser resolution with the AMD simulation models.提示：由于大部分仿真时间都花在 delta 周期上，因此在 AMD 仿真模型中使用更粗的分辨率不会显著提高仿真器性能。

There is no need to use a finer resolution, such as femtoseconds (fs) as some simulators will round the numbers while others will truncate the numbers.没有必要使用更精细的分辨率，如飞秒 (fs)，因为有些仿真器会对数字进行四舍五入，而有些则会截断数字。

Functional Simulation Early in the Design Flow
在设计流程早期进行功能仿真

Use functional or register transfer level (RTL) simulation to verify syntax and functionality. This first pass simulation is typically performed to verify the RTL or behavioral code and to confirm that the design is functioning as intended.
使用功能或寄存器传输层 (RTL) 仿真来验证语法和功能。执行第一道仿真通常是为了验证 RTL 或行为代码，并确认设计是否按预期运行。

With larger hierarchical designs, you can simulate individual IP, block designs, or hierarchical modules before testing your complete design. This simulation process makes it easier to debug your code in smaller portions before examining the larger design.
When each module simulates as expected, create a top-level design test bench to verify that your entire design functions as planned. Use the same test bench again for the final timing simulation to confirm that your design functions as expected under worst-case delay conditions.对于较大的分层设计，您可以在测试完整设计之前对单个 IP、块设计或分层模块进行仿真。这种仿真过程可以让您在检查大型设计之前，更轻松地调试小部分代码。
当每个模块都按预期进行仿真时，创建一个顶层设计测试台来验证整个设计是否按计划运行。再次使用相同的测试台进行最终时序仿真，以确认设计在最坏延迟条件下的功能符合预期。

RECOMMENDED: At this stage, no timing information is provided. AMD recommends performingsimulation in unit-delay mode to avoid the possibility of a race condition.建议：在这一阶段，没有提供时序信息。AMD 建议在单元延迟模式下进行仿真，以避免出现竞争条件的可能性。

You should use synthesizable HDL constructs for the initial design creation. Do not instantiate specific components unless necessary. This allows for:
在创建初始设计时，应使用可综合的 HDL 结构。除非必要，否则不要实例化特定组件。这样可以
• More readable code- 代码更易读
• Faster and simpler simulation- 更快、更简单的仿真
• Code portability (the ability to migrate to different device families)

• 代码可移植性（能够移植到不同的器件系列）
  • Code reuse (the ability to use the same code in future designs)
• 代码重用（能够在未来的设计中使用相同的代码）

TIP: You might need to instantiate components if the components cannot be inferred.提示：如果无法推断出组件，则可能需要实例化组件。

Instantiation of components can make your design code architecture specific.组件的实例化会使你的设计代码具有特定的架构。

Using Structural Netlists for Simulation使用结构网表进行仿真

After synthesis or implementation, you can perform netlist simulation in functional or timing mode. The netlist simulation can also help you with the following:
综合或实现后，您可以在功能或时序模式下执行网表仿真。网表仿真还可以帮助您完成以下工作：
• Identify post-synthesis and post-implementation functionality changes caused by:- 确定综合后和实现后功能变化的原因：
○ Synthesis attributes or constraints that create mismatches (such as full_case and parallel_case)造成不匹配的综合属性或约束
○ UNISIM attributes applied in the Xilinx Design Constraints (XDC) file
Xilinx 设计约束 (XDC) 文件中应用的 UNISIM 属性
○ Differences in language interpretation between synthesis and simulation综合与仿真之间的语言解释差异
○ Dual-port RAM collisions 双端口 RAM 冲突
○ Missing or improperly applied timing constraints时序约束缺失或应用不当
○ Operation of asynchronous paths异步路径的操作
○ Functional issues due to optimization techniques优化技术导致的功能问题
• Sensitize timing paths declared as false or multi-cycle during STA- 在 STA 期间敏感化被声明为错误或多周期的时序路径
• Generate netlist switching activity to estimate power- 生成网表开关活动以估算功耗
• Identify X state pessimism- 识别 X 状态悲观
For netlist simulation, you can use one or more of the libraries shown in the following table.对于网表仿真，您可以使用下表所示的一个或多个库。
The UNIFAST library is an optional library that you can use during functional simulation to speed up simulation runtime.
UNIFAST libraries are supported for 7 series devices only. UltraScale and later device architectures do not support UNIFAST libraries, because all the optimizations are incorporated in the UNISIM libraries by default. For more information on AMD simulation libraries, see this link in the Vivado Design Suite User Guide: Logic Simulation (UG900).
UNIFAST 库是一个可选库，可在功能仿真期间使用，以加快仿真运行时间。UNIFAST 库仅支持 7 系列器件。UltraScale 及更高器件架构不支持 UNIFAST 库，因为所有优化都默认集成在 UNISIM 库中。
默认情况下，所有优化都包含在 UNISIM 库中。有关 AMD 仿真库的更多信息，请参阅《Vivado 设计套件用户指南》中的此链接： 逻辑仿真 (UG900) 中的链接。

Primitives/elements of the UNISIM library do not have any timing information except the clocked elements. To prevent race conditions during functional simulation, clocked elements have a clock-to-out delay of 100 ps. Waveform views might show spikes and glitches for combinatorial signals, due to lack of any delay in the UNISIM elements.UNISIM 库中的基元/元素没有任何时序信息，但时钟元素除外。为防止功能仿真过程中出现竞争条件，时钟元素的时钟到输出延迟为 100 ps。由于 UNISIM 元素没有任何延迟，波形视图可能会显示组合信号的尖峰和突波。

Timing Simulation时序仿真

AMD supports timing simulation in Verilog only. You can export a netlist for timing simulation from an open synthesized or implemented design using the File → Export → Export Netlist command in the Vivado IDE, or by using the write_verilog Tcl command.
AMD 仅支持 Verilog 时序仿真。您可以使用 Vivado IDE 中的文件 → 导出 → 导出网表命令，或使用 write_verilog Tcl 命令，从已综合或已实现的开放设计中导出网表进行时序仿真。

The Verilog system task $sdf_annotate within the simulation netlist specifies the name of the standard delay format (SDF) file to be read for timing delays. This directive is added to the exported netlist when the -sdf_anno option is enabled on the Netlist tab of the Simulation Settings dialog box in the Vivado IDE. The SDF file can be written with the write_sdf command. The Vivado simulator automatically reads the SDF file during the compilation step.
仿真网表中的 Verilog 系统任务 $sdf_annotate 指定了要读取的时序延迟标准延迟格式 (SDF) 文件的名称。在 Vivado IDE 的 "仿真设置 "对话框的 "网表 "选项卡上启用 -sdf_anno 选项后，该指令将添加到导出的网表中。可以使用 write_sdf 命令写入 SDF 文件。Vivado 仿真器会在编译步骤中自动读取 SDF 文件。

TIP: The Vivado simulator supports mixed-language simulation, which means that if you are a VHDL user,you can generate a Verilog simulation netlist and instantiate it from the VHDL test bench.提示：Vivado 仿真器支持混合语言仿真，这意味着如果您是 VHDL 用户，则可以生成 Verilog 仿真网表并从 VHDL 测试台将其实例化。

Many users do not run timing simulation due to high runtime. However, you should consider using full timing simulation because it is the closest method of modeling hardware behavior. If your design does not work on hardware, it is much easier to debug the failure in simulation, as long as you have a timing simulation that can reproduce the failure.由于运行时间较长，许多用户并不运行时序仿真。但是，您应该考虑使用全时序仿真，因为它是最接近硬件行为的建模方法。如果您的设计无法在硬件上运行，那么只要您的时序仿真能重现故障，那么在仿真中调试故障就会容易得多。

If you decide to skip timing simulation, you should make sure of the following:
如果决定跳过时序仿真，则应确保以下几点：
• Ensure that your STA constraints are absolutely correct. Pay special attention to exceptions.
- 确保您的 STA 约束绝对正确。特别注意例外情况。
• Ensure that your netlist is exactly equivalent to what you intended through your RTL. Pay special attention to any inference-related information provided by the synthesis tool.
- 确保您的网表完全等同于您在 RTL 中的意图。特别注意综合工具提供的任何推理相关信息。

Simulation Flow仿真流程

The Vivado Design Suite supports both integrated simulation, which allows you to run the simulator from within the Vivado IDE, and batch simulation, which allows you to generate a script from the Vivado tools to run simulation on an external verification environment.Vivado 设计套件支持集成仿真和批量仿真，集成仿真允许您在 Vivado IDE 中运行仿真器，批量仿真允许您从 Vivado 工具生成脚本，在外部验证环境中运行仿真。

Integrated Simulation集成仿真

The Vivado IDE provides full integration with the Vivado simulator, and all supported third-party simulators. In this flow, the simulator is called from within the Vivado IDE, and you can compile and simulate the design easily with a push of a button, or with the launch_simulation Tcl command.
Vivado 集成开发环境可与 Vivado 仿真器和所有受支持的第三方仿真器完全集成。在此流程中，仿真器在 Vivado IDE 中调用，您只需按下按钮或使用 launch_simulation Tcl 命令即可轻松编译和仿真设计。

IMPORTANT! The launch_simulation command launches integrated simulation for project-based designs. This command does not support Non-Project Mode.重要！launch_simulation 命令针对基于项目的设计启动集成仿真。该命令不支持非项目模式。

For information on the steps involved in setting up the integrated simulation flow, see this link in the Vivado Design Suite User Guide: Logic Simulation (UG900).有关设置集成仿真流程步骤的信息，请参阅《Vivado 设计套件用户指南》中的此链接： 逻辑仿真 (UG900)》中的链接。

Batch Simulation批处理仿真

RECOMMENDED: If your verification environment has a self-checking test bench, run simulation in batch mode. There is a significant runtime cost when you view simulator waveforms using the integrated simulation.建议：如果您的验证环境有自检测试台，请在批处理模式下运行仿真。使用集成仿真查看仿真器波形时会产生大量运行时间成本。

For batch simulation, the Vivado Design Suite provides the export_simulation Tcl command to generate simulation scripts for supported simulators, including the Vivado simulator. You can use the scripts generated by export_simulation directly or use the scripts as a reference for building your own custom simulation scripts.对于批量仿真，Vivado Design Suite 提供 export_simulation Tcl 命令，用于为支持的仿真器（包括 Vivado 仿真器）生成仿真脚本。您可以直接使用 export_simulation 生成的脚本，也可以将这些脚本作为构建自己的自定义仿真脚本的参考。

The export_simulation command creates separate scripts for each stage of the simulation process (compile, elaborate, and simulate) so that you can easily incorporate the generated scripts in your own verification flow. For more information about generating scripts for batch simulation, see this link in the Vivado Design Suite User Guide: Logic Simulation (UG900).

export_simulation 命令会为仿真过程的每个阶段（编译、阐述和仿真）创建单独的脚本，这样您就可以轻松地将生成的脚本纳入自己的验证流程。有关为批量仿真生成脚本的更多信息，请参阅《Vivado 设计套件用户指南》中的此链接： 逻辑仿真 (UG900) 中的链接。

8、Running Logic Synthesis and Implementation（逻辑综合和逻辑实现）

Logic Synthesis逻辑综合

Vivado synthesis enables you to configure, launch, and monitor synthesis runs. The Vivado IDE displays the synthesis results and creates report files. You can select synthesis warnings and errors from the Messages window to highlight the logic in the RTL source files.Vivado 综合可让您配置、启动和监控综合运行。Vivado IDE 会显示综合结果并创建报告文件。您可以从 "信息 "窗口选择综合警告和错误，以突出显示 RTL 源文件中的逻辑。

You can launch multiple synthesis runs concurrently or serially. On a Linux system, you can launch runs locally or on remote servers. With multiple synthesis runs, Vivado synthesis creates multiple netlists that are stored with the Vivado Design Suite project. You can open different versions of the synthesized netlist in the Vivado IDE to perform device and design analysis. You can also create constraints for I/O pin planning, timing, floorplanning, and implementation. The most comprehensive list of DRCs is available after a synthesized netlist is produced, when clock and clock logic are available for analysis and placement.您可以同时或连续启动多个综合运行。在 Linux 系统上，可以在本地或远程服务器上启动运行。通过多个综合运行，Vivado 综合会创建多个网表，这些网表与 Vivado Design Suite 项目一起存储。您可以在 Vivado IDE 中打开不同版本的综合网表，以执行器件和设计分析。您还可以为 I/O 引脚规划、时序、平面规划和实现创建约束。综合网表制作完成后，当时钟和时钟逻辑可用于分析和布局时，可使用最全面的 DRC 列表。

For more information, see the Vivado Design Suite User Guide: Synthesis (UG901).

Note: Launching multiple jobs simultaneously on the same machine can exhaust memory, resulting in random Vivado crashes. Ensure to reserve enough memory for all jobs running on a single machine.注意：在同一台机器上同时启动多个作业可能会耗尽内存，导致 Vivado 随机崩溃。确保为单台机器上运行的所有作业预留足够的内存。

Implementation实现

Vivado implementation enables you to configure, launch, and monitor implementation runs. You can experiment with different implementation options and create your own reusable strategies for implementation runs. For example, you can create strategies for quick runtimes, improved system performance, or area optimization. As the runs complete, implementation run results display and report files are available.Vivado 实现使您能够配置、启动和监控实现运行。您可以尝试不同的实现选项，并为实现运行创建自己的可重用策略。例如，您可以创建快速运行时间、改进系统性能或优化面积的策略。运行完成后，将显示实施运行结果并提供报告文件。

You can launch multiple implementation runs either simultaneously or serially. On a Linux system,you can use remote servers. You can create constraint sets to experiment with various timing constraints, physical constraints, or alternate devices. 您可以同时或连续启动多个执行运行。在 Linux 系统上，可以使用远程服务器。您可以创建约束集来试验各种时序约束、物理约束或备用器件。

For more information, see the Vivado Design Suite User Guide: Implementation (UG904) and Vivado Design Suite User Guide: Using
Constraints (UG903).有关详细信息，请参阅《Vivado 设计套件用户指南》： 实现 (UG904) 和《Vivado 设计套件用户指南》： 使用约束 (UG903)。

TIP: You can add Tcl scripts to be sourced before and after synthesis, any stage of implementation, or bitstream generation using the tcl.pre and
tcl.post files. For more information, see the Vivado Design Suite User Guide: Using Tcl Scripting (UG894).提示：您可以使用 tcl.pre 和 tcl.post 文件添加 Tcl 脚本。有关详细信息，请参阅《Vivado 设计套件用户指南》： 使用 Tcl 脚本 (UG894)。

Note: Launching multiple jobs simultaneously on the same machine can exhaust memory, resulting in random Vivado crashes. Ensure to reserve enough memory for all jobs running on a single machine.注意：在同一台机器上同时启动多个作业可能会耗尽内存，导致 Vivado 随机崩溃。确保为单台机器上运行的所有作业预留足够的内存。

Configuring Synthesis and Implementation Runs
配置综合和执行运行

When using Project Mode, various settings are available to control the features of synthesis and implementation. These settings are passed to runs using run strategies, which you set in the Settings dialog box. A run strategy is simply a saved set of run configuration parameters. AMD supplies several pre-defined run strategies for running synthesis and implementation, or you can apply custom run settings. In addition, you can use separate constraint sets for synthesis and implementation.使用项目模式时，可以使用各种设置来控制综合和实现功能。这些设置通过运行策略传递给运行，您可以在 "设置 "对话框中进行设置。运行策略只是一组已保存的运行配置参数。AMD 提供了几种预定义的运行策略，用于运行综合和实现，您也可以应用自定义的运行设置。此外，您还可以为综合和实现使用单独的约束集。

For information on modifying settings, see Using Synthesis Settings in the Vivado Design Suite User Guide: Synthesis (UG901) and see this link in the Vivado Design Suite User Guide: Implementation (UG904).有关修改设置的信息，请参阅《Vivado 设计套件用户指南中的 “使用综合设置”： 综合》(UG901) 中的 "使用综合设置 "和《Vivado Design Suite 用户指南》(UG904) 中的 "实现 "链接： 实现 (UG904) 中的链接。

TIP: You can create an out-of-context module run to synthesize the Vivado Design Suite IP in the project. If you generate a design checkpoint for the IP, the default behavior is to create an out-of-context run for each IP in the design.提示：您可以创建上下文外模块运行来综合项目中的 Vivado Design Suite IP。如果为 IP 生成设计检查点，默认行为是为设计中的每个 IP 创建一个上下文外运行。

Creating and Managing Runs创建和管理运行

After the synthesis and implementation settings are configured in the Settings dialog box, you can launch synthesis or implementation runs using any of the following methods:
在 "设置 "对话框中配置综合和实现设置后，可以使用以下任一方法启动综合或实现运行：
• In the Flow Navigator, select Run Synthesis, Run Implementation, or Generate Bitstream or Generate Device Image for Versal adaptive SoC.- 在 "流程导航器 "中，选择 “运行综合”、"运行实现 "或 "生成位流 "或 生成 Versal 自适应 SoC 的器件映像。
• In the Design Runs window, select a run, right-click, and select Launch Runs. Alternatively,you can click the Launch Selected Runs button.- 在 "设计运行 "窗口中，选择一个运行，右键单击并选择 “启动运行”。或者也可以单击 "启动所选运行 "按钮。
• Select Flow → Run Synthesis, Flow → Run Implementation, or Flow → Generate Bitstream or Generate Device Image for Versal adaptive SoC.

• 选择 Flow → Run Synthesis、Flow → Run Implementation 或 Flow → Generate Bitstream 或 Generate Device Image for Versal adaptive SoC。

You can create multiple synthesis or implementation runs to experiment with constraints or tool settings. To create additional runs:
您可以创建多个综合或实现运行，以试验约束或工具设置。要创建其他运行，请执行以下操作

1. In the Flow Navigator, right-click Synthesis or Implementation.
2. Select Create Synthesis Runs or Create Implementation Runs.
3. In the Create New Runs wizard (see the following figure), select the constraint set and target part.
4. 在流程导航器中，右键单击综合或实现。
5. 选择创建综合运行或创建实现运行。
6. 在创建新运行向导中（见下图），选择约束集和目标器件。

If more than one synthesis run exists, you can also select the netlist when creating implementation runs. You can then create one or more runs with varying strategies, constraint sets, or devices. There are several launch options available when multiple runs exist. You can launch selected runs sequentially or in parallel on multiple local processors.
如果存在多个综合运行，也可以在创建实现运行时选择网表。然后，您可以创建一个或多个具有不同策略、约束集或器件的运行。当存在多个运行时，有多种启动选项可供选择。您可以在多个本地处理器上顺序或并行启动选定的运行。

TIP: You can configure and use remote hosts on Linux systems only
提示：只能在 Linux 系统上配置和使用远程主机

Managing Runs with the Design Runs Window使用 "设计运行 "窗口管理运行

The Design Runs windows (shown in the following figure) displays run status and information and provides access to run management commands in the popup menu. You can manage multiple runs from the Design Runs window. When multiple runs exist, the active run is displayed in bold.设计运行 "窗口（如下图所示）显示运行状态和信息，并在弹出菜单中提供运行管理命令。您可以从 "设计运行 "窗口管理多个运行。存在多个运行时，活动运行以粗体显示。

The Vivado IDE displays the design information for the active run. The Project Summary, reports, and messages all reflect the results of the active run.Vivado IDE 会显示活动运行的设计信息。项目摘要、报告和信息都反映了当前运行的结果。

The Vivado IDE opens the active design by default when you select Open Synthesized Design or Open Implemented Design in the Flow Navigator.
在流程导航器中选择 "打开合成设计 "或 "打开已实现设计 "时，Vivado IDE 默认打开活动设计。

You can make a run the active run using the Make Active popup menu command. The Vivado IDE updates results to reflect the information
about the newly designated active run. 您可以使用 Make Active（激活）弹出式菜单命令将运行设为活动运行。Vivado IDE 会更新结果以反映新指定的活动运行的信息。
Double-click any synthesized or implemented run to open the design in the Vivado IDE.
双击任何已合成或已实现的运行可在 Vivado IDE 中打开设计。

Resetting Runs重置运行

In the Flow Navigator, you can right-click Synthesis or Implementation, and use the following popup menu commands to reset runs. For more information, see this link in the Vivado Design Suite User Guide: Implementation (UG904).
在流程导航器中，您可以右键单击合成或实现，然后使用以下弹出式菜单命令重置运行。有关详细信息，请参阅《Vivado Design Suite 用户指南》中的此链接： 实现 (UG904)。
• Reset Runs: Resets the run to its original state and optionally deletes generated files from the run directory.- 重置运行：将运行重置为原始状态，并可选择删除运行目录中生成的文件。
• Reset to Previous Step: Resets the run to the listed step.- 重置到上一步： 将运行重置到列出的步骤。

TIP: To stop an in-process run, click the Cancel button in the upper right corner of the Vivado IDE.提示：要停止进程中的运行，请单击 Vivado IDE 右上角的取消按钮。

Launching Runs on Remote Clusters在远程集群上启动运行

To launch runs on remote Linux hosts, you can directly access a load sharing facility (LSF) server farm. Vivado allows all cluster commands to be configured through Tcl. For more information, see Using Remote Hosts and Compute Clusters in the Vivado Design Suite User Guide: Implementation
(UG904).要在远程 Linux 主机上启动运行，可以直接访问负载分担设施（LSF）服务器群。Vivado 允许通过 Tcl 配置所有集群命令。有关详细信息，请参阅《Vivado 设计套件用户指南》中的 “使用远程主机和计算集群”： 实现
(UG904).

Performing Implementation with Incremental Compile使用增量编译执行

You can specify the incremental compile flow when running Vivado implementation to facilitate small design changes.
Incremental compile can reduce place and route runtimes and preserve existing implementation results depending on the scope of the change and the amount of timing-critical logic that is modified.
在运行 Vivado 实现时，您可以指定增量编译流程，以方便进行小的设计更改。
增量编译可减少布局布线运行时间，并保留现有实现结果，具体取决于更改范围和修改的时序关键逻辑的数量而定。

You can specify the Set Incremental Compile option in the Implementation Settings dialog box in the Vivado IDE, or by using the Set Incremental Compile command from the right-click menu of the Design Runs window. You can also use the read_checkpoint Tcl command with the - incremental option, and point to a routed design checkpoint to use as a reference. For more information, see this link in the Vivado Design Suite User Guide: Implementation (UG904).
您可以在 Vivado IDE 的 "实现设置 "对话框中指定 "设置增量编译 "选项，或使用 "设计运行 "窗口右键菜单中的 "设置增量编译 "命令。您还可以使用带有 - 增量选项的 read_checkpoint Tcl 命令，并指向路由设计检查点作为参考。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接： 实现 (UG904) 中的链接。

Closing Timing Using Intelligent Design Runs使用智能设计运行关闭时序

Intelligent design runs (IDR) uses a multi-stage run approach to automatically close timing on a design. This flow can be invoked in the GUI by right clicking on implementation run in the design runs window and selecting “Close Timing Using Intelligent Design Runs” or in Tcl, by creating a
new run using the IDR flow and properly setting the reference run. For information on Intelligent design runs, see Chapter 8 of Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
智能设计运行 (IDR) 采用多阶段运行方法自动关闭设计时序。在图形用户界面中，可以右键单击设计运行窗口中的实现运行，然后选择 “使用智能设计运行关闭时序”；在 Tcl 中，也可以使用 IDR 流程创建一个新运行，并正确设置参考运行。或在 Tcl 中使用 IDR 流程创建新运行并正确设置参考运行。有关智能设计运行的信息，请参见《Vivado 设计套件用户指南》第 8 章： 设计分析和关闭技术》(UG906) 第 8 章。

**Implementing Engineering Change Orders (ECOs)**实施工程变更单 (ECO)

Engineering change orders (ECOs) are modifications to an implemented design, with the intent to minimize impact to the original design. The Vivado Design Suite provides an ECO flow, which lets you modify an existing design checkpoint to implement changes, run reports on the changed netlist, and generate the required bitstream files.
工程变更单 (ECO) 是对已实施设计的修改，目的是尽量减少对原始设计的影响。Vivado 设计套件提供了一个 ECO 流程，可让您修改现有的设计检查点以实现变更、对变更后的网表运行报告并生成所需的比特流文件。

The advantage of the ECO flow is fast turn-around time by taking advantage of the incremental place and route features of the Vivado tool. The Vivado IDE provides a predefined layout to support the ECO flow. Refer to this link in the Vivado Design Suite User Guide: Implementation(UG904) for more information.
ECO 流程的优势在于利用 Vivado 工具的增量布局布线功能快速缩短周转时间。Vivado IDE 提供了支持 ECO 流程的预定义布局。请参阅《Vivado 设计套件用户指南》中的此链接： 实现(UG904) 中的链接了解更多信息。

9、Viewing Log Files, Messages, Reports, and Properties（查看log文件，消息，报告，属性）

Viewing Log Files

In the Log window (shown in the following figure), you can click the different tabs to view the standard output for Synthesis, Implementation, and Simulation. This output is also included in the vivado.log file that is written to the Vivado IDE launch directory.
在日志窗口（如下图所示）中，可以单击不同的选项卡查看合成、实现和仿真的标准输出。这些输出也包含在写入 Vivado IDE 启动目录的 vivado.log 文件中。

Viewing Messages查看信息窗口

In the Messages window (shown in the following figure), messages are categorized according to design step and severity level: Errors, Critical Warnings, Warnings, Info, and Status. To filter messages, select the appropriate check boxes in the window header. You can expand the
message categories to view specific messages. You can click the Collapse All icon to show only the main design steps. This enables better navigation to specific messages. Many messages include links that take you to logic lines in the RTL files. For more information, including advanced filtering techniques, see this link in the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).
在 "信息 "窗口（如下图所示）中，信息根据设计步骤和严重程度进行分类： 错误、严重警告、警告、信息和状态。要过滤信息，请选择窗口标题中相应的复选框。您可以展开查看特定的信息。您可以单击 "全部折叠 "图标，只显示主要设计步骤。这样可以更好地导航到特定的信息。许多信息都包含指向 RTL 文件中逻辑行的链接。有关更多信息，包括高级过滤技术，请参阅《Vivado 设计套件用户指南中的此链接： 使用 Vivado IDE (UG893)》中的链接。

Viewing Reports查看报告

In the Reports window (shown in the following figure), several standard reports are generated using the launch_runs Tcl commands. You can double-click any report to display it in the Vivado IDE Text Editor. You can also create custom reports using Tcl commands in the Tcl Console or using report strategies.
For more information, see this link and this link in the Vivado
Design Suite User Guide: Using the Vivado IDE (UG893) and see this link and this link in Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
在报告窗口（如下图所示）中，将使用 launch_runs Tcl 命令生成多个标准报告。您可以双击任何报告，将其显示在 Vivado IDE 文本编辑器中。您还可以使用 Tcl 控制台中的 Tcl 命令或报告策略创建自定义报告。
有关详细信息，请参阅《Vivado设计套件用户指南》中的此链接和此链接： 使用 Vivado IDE (UG893)》中的此链接和此链接，以及《Vivado Design Suite 用户指南》中的此链接和此链接： 设计分析和封闭技术 (UG906) 中的此链接和此链接。

Viewing or Editing Device Properties查看或编辑设备属性

With the elaborated, synthesized, or implemented design open, you can use the Tools → Edit Device Properties command to open the Edit Device Properties dialog box (shown in the following figure) in which you can view and set device configuration and bitstream-related properties. This command is available only when a design is open. For information on each property, see the link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).
打开已详细设计、综合设计或已实现的设计后，可以使用工具 → 编辑器件属性命令打开编辑器件属性对话框（如下图所示），在该对话框中可以查看和设置器件配置以及与位流相关的属性。该命令仅在设计打开时可用。有关各属性的信息，请参阅《Vivado 设计套件用户指南》中的链接： 编程和调试 (UG908) 中的链接。

For information on setting device configuration modes, see this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
有关设置器件配置模式的信息，请参阅《Vivado 设计套件用户指南》中的此链接： I/O 和时钟规划 (UG899) 中的链接。

Note: The Edit → Device Properties is only available when a design is open.
注意：编辑 → 设备属性仅在设计打开时可用。

10、Opening Designs to Perform Design Analysis and Constraints Definition（打开设计，然后执行设计分析和约束定义）

You can perform design analysis and assign constraints after RTL elaboration, after synthesis, or after implementation.
您可以在 RTL 详细设计后、综合后或实现后执行设计分析和分配约束。
To identify design issues early, you can perform design analysis prior to implementation, including timing simulation, resource estimation, connectivity analysis, and DRCs.
为了及早发现设计问题，可以在实现之前执行设计分析，包括时序仿真、资源估算、连接分析和 DRC。
You can open the various synthesis or implementation run results for analysis and constraints assignment. This is known as opening the design.
您可以打开各种综合或实现运行结果进行分析和约束分配。这就是所谓的打开设计。

When you open the design, the Vivado IDE compiles the netlist and applies physical and timing constraints against a target part. You can open, save, and close designs. 打开设计时，Vivado IDE 会编译网表，并针对目标器件应用物理和时序约束。您可以打开、保存和关闭设计。

When you open a new design, you are prompted to close any previously opened designs to preserve memory. However, you are not required to close the designs, because multiple designs can be opened simultaneously. 打开新设计时，系统会提示您关闭之前打开的任何设计以保留内存。不过，您不必关闭设计，因为可以同时打开多个设计。

When you open a synthesized design, the Vivado IDE displays the netlist and constraints. When you open an implemented design, the Vivado IDE displays the netlist, constraints, and implementation results. The design data is presented in different forms in different windows, and you can cross probe and coordinate data between windows.
打开综合设计时，Vivado IDE 会显示网表和约束。打开已实现的设计时，Vivado IDE 会显示网表、约束和实现结果。设计数据以不同的形式显示在不同的窗口中，您可以在窗口之间交叉探测和协调数据。

After opening a design, many analysis and reporting features are available in the Vivado IDE. 打开设计后，Vivado IDE 中提供了许多分析和报告功能。

For example, you can analyze device resources in the graphical windows of the internal device and the external physical package. You can also apply and analyze timing and physical constraints in the design using the Netlist, Device, Schematic, or Hierarchy windows. 例如，您可以在内部器件和外部物理封装的图形窗口中分析器件资源。您还可以使用网表、器件、原理图或层次结构窗口应用和分析设计中的时序和物理约束。

For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) and Vivado Design Suite User Guide: Using Constraints (UG903).有关详细信息，请参阅《Vivado 设计套件用户指南》： 设计分析和封闭技术 (UG906) 和 Vivado 设计套件用户指南： 使用约束 (UG903)。

Note: If you make constraint changes while the design is open, you are prompted to save the changes to the original XDC source files or to create a new constraint set. For more information, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).注意：如果在设计打开时更改约束，系统会提示您将更改保存到原始 XDC 源文件或创建新约束集。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接： 系统级设计输入 (UG895)。

Opening an Elaborated RTL Design打开详细设计的 RTL 设计

When you open an elaborated design, the Vivado Design Suite expands and compiles the RTL netlist and applies physical and timing constraints against a target part. The different elements of the elaborated design are loaded into memory, and you can analyze and modify the elements as needed to complete the design. For more information, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
打开详细设计时，Vivado 设计套件会展开和编译 RTL 网表，并针对目标器件应用物理和时序约束。详细设计的不同元素会加载到内存中，您可以根据需要分析和修改这些元素，以完成设计。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接： 系统级设计输入 (UG895)。

The Vivado Design Suite includes linting DRCs and checking tools that enable you to analyze your design for logic correctness.
You can make sure that there are no logic compilation issues, no missing modules, and no interface mismatches.
In the Messages window, you can click links in the messages to display the problem lines in the RTL files in the Vivado IDE Text Editor. In the Schematic window, you can explore the logic interconnects and hierarchy in a variety of ways.
Vivado 设计套件包括可让您分析设计逻辑正确性的线性 DRC 和检查工具。
您可以确保不存在逻辑编译问题、模块缺失或接口不匹配。
在 "信息 "窗口中，您可以单击信息中的链接，以在 Vivado IDE 文本编辑器中显示 RTL 文件中的问题行。在 "原理图 "窗口中，您可以通过多种方式探索逻辑互连和层次结构。

The Schematic window displays RTL interconnects using RTL-based logic constructs. You can select logic in the Schematic window and see specific lines in the RTL files in the Vivado IDE Text Editor. For more information, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
原理图窗口使用基于 RTL 的逻辑结构显示 RTL 互连。您可以在示意图窗口中选择逻辑，并在 Vivado IDE 文本编辑器中查看 RTL 文件中的特定行。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接： 系统级设计输入 (UG895)。

Note: There is no FPGA technology mapping during RTL elaboration.
注：在 RTL 详细设计过程中没有 FPGA 技术映射。

Constraints that are defined on specific logic instances within the logic hierarchy, such as registers, might not be resolvable during RTL elaboration. The logic names and hierarchy generated during elaboration might not match those generated during synthesis.
在 RTL 详细设计过程中，对逻辑层次结构中特定逻辑实例（如寄存器）定义的约束可能无法解决。详细设计过程中生成的逻辑名称和层次结构可能与综合过程中生成的名称和层次结构不一致。

For this reason, you might see constraint mapping warnings or errors when elaborating the RTL design, if you have these types of constraints defined. However, when you run synthesis on the design, these issues are resolved.
因此，如果定义了这些类型的约束，在详细设计 RTL 时可能会看到约束映射警告或错误。不过，在对设计进行综合时，这些问题就会得到解决。

Using the I/O planning capabilities of the Vivado IDE, you can interactively configure and assign I/O Ports in the elaborated RTL design and run DRCs. When possible, it is recommended that you perform I/O planning after synthesis.
使用 Vivado IDE 的 I/O 规划功能，您可以在详细的 RTL 设计中交互式地配置和分配 I/O 端口，并运行 DRC。在可能的情况下，建议您在综合后执行 I/O 规划。
This ensures proper clock and logic constraint resolution, and the DRCs performed after synthesis are more extensive. For more information,
see Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
这可确保正确的时钟和逻辑约束解析，而且合成后执行的 DRC 更为广泛。*有关更多信息，请参阅《Vivado 设计套件用户指南：综合》、请参阅《Vivado 设计套件用户指南》： I/O 和时钟规划 (UG899)。

TIP: When you select the Report DRC command, the Vivado IDE invokes a set of RTL and I/O DRCs to identify logic issues such as asynchronous clocks, latches, and so forth. For more information, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
提示：当您选择报告 DRC 命令时，Vivado IDE 会调用一组 RTL 和 I/O DRC 来识别逻辑问题，如异步时钟、锁存等。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接： 系统级设计输入 (UG895)。

To open an elaborated design, use one of the following methods:
要打开详细设计，请使用以下方法之一：
• In the RTL Analysis section of the Flow Navigator, select Open Elaborated Design.- 在流程导航器的 RTL 分析部分，选择打开详细设计。
• In the Flow Navigator, right-click RTL Analysis, and select New Elaborated Design from the popup menu.- 在流程导航器中，右键单击 RTL 分析，从弹出菜单中选择新建详细设计。
• Select Flow → Open Elaborated Design.- 选择 Flow → Open Elaborated Design。

The following figure shows the default view layout for an open elaborated RTL design. Notice the logic instance that was cross-selected from the schematic to the specific instance in the RTL source file and within the elaborated RTL netlist.
下图显示了开放式详细 RTL 设计的默认视图布局。请注意从原理图交叉选择到 RTL 源文件和详细 RTL 网表中特定实例的逻辑实例。

Opening a Synthesized Design

When you open a synthesized design, the Vivado Design Suite opens the synthesized netlist and applies physical and timing constraints against a target part.
The different elements of the synthesized design are loaded into memory, and you can analyze and modify these elements as needed to complete the design. You can save updates to the constraints files, netlist, debug cores, and configuration.
打开综合设计时，Vivado 设计套件会打开综合网表，并针对目标器件应用物理和时序约束。
综合设计的不同元素会加载到内存中，您可以根据需要分析和修改这些元素，以完成设计。您可以保存对约束文件、网表、调试核和配置的更新。

In a synthesized design, you can perform many design tasks, including early timing, power, and utilization estimates that can help you determine if your design is converging on desired targets.
在综合设计中，您可以执行许多设计任务，包括早期时序、功耗和利用率估算，这可以帮助您确定设计是否正在向预期目标靠拢。
You can explore the design in a variety of ways using the windows in the Vivado IDE. Objects are always cross-selected in all other windows.
您可以使用 Vivado IDE 中的窗口以多种方式探索设计。在所有其他窗口中，对象总是交叉选择的。
You can cross probe to problem lines in the RTL files from various windows, including the Messages, Schematic, Device, Package, and Find windows.The Schematic window allows you to interactively explore the logic interconnect and hierarchy.
您可以从各种窗口（包括 “信息”、“原理图”、“器件”、"封装 "和 "查找 "窗口）交叉探测 RTL 文件中的问题行。"原理图 "窗口允许您交互式地探索逻辑互连和层次结构。
You can also apply timing constraints and perform further timing analysis. In addition, you can interactively define physical constraints for I/O ports, floorplanning, or design configuration. For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
您还可以应用时序约束并执行进一步的时序分析。此外，您还可以交互式定义 I/O 端口、平面规划或设计配置的物理约束。有关详细信息，请参阅《Vivado 设计套件用户指南》： 设计分析和封闭技术 (UG906)。

Using the I/O planning capabilities of the Vivado IDE, you can interactively configure and assign I/O ports in the synthesized design and run DRCs. Select the Run DRC command to invoke a comprehensive set of DRCs to identify logic issues. For more information, see this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899) and see this link in Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
使用 Vivado IDE 的 I/O 规划功能，您可以在综合设计中交互式配置和分配 I/O 端口，并运行 DRC。选择 "运行 DRC "命令可调用一组全面的 DRC 来识别逻辑问题。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接： I/O 和时钟规划 (UG899) 中的此链接，以及 Vivado Design Suite 用户指南中的此链接： 设计分析和封闭技术 (UG906) 中的链接。
You can configure and implement debug core logic in the synthesized design to support test and debug of the programmed device. In the Schematic or Netlist windows, interactively select signals for debug. 您可以在综合设计中配置和实施调试核心逻辑，以支持对已编程器件的测试和调试。在原理图或网表窗口中，交互式选择调试信号。

Debug cores are then configured and inserted into the design. The core logic and interconnect is preserved through synthesis updates of the design when possible. For more information, see this link in the Vivado Design Suite User Guide: Programming and Debugging(UG908).
然后配置调试核心并将其插入设计中。在可能的情况下，内核逻辑和互连会通过设计的综合更新得以保留。更多信息请参阅《Vivado 设计套件用户指南》中的此链接： 编程和调试》（UG908）中的链接。
To open a synthesized design, use one of the following methods:
• In the Synthesis section of the Flow Navigator, select Open Synthesized Design.
• In the Flow Navigator, right-click Synthesis, and select New Synthesized Design from the popup menu.
• Select Flow → Open Synthesized Design.
• In the Design Runs view, double-click the run name.
要打开合成设计，请使用以下方法之一：

• 在流程导航器的合成部分，选择打开合成设计。
• 在流程导航器中，右键单击合成，从弹出菜单中选择新建合成设计。
• 选择流程 → 打开合成设计。
• 在设计运行视图中，双击运行名称。

The following figure shows the default view layout for an open synthesized design.
下图显示了开放综合设计的默认视图布局。

Opening an Implemented Design

When you open an implemented design in the Flow Navigator, the Vivado IDE opens the implemented netlist and applies the physical and timing constraints used during implementation, placement, and routing results against the implemented part. The placed logic and routed connections of the implemented design are loaded into memory, and you can analyze and modify the elements as needed to complete the design. You can save updates to the constraints files, netlist, implementation results, and design configuration. Because the Vivado IDE allows for multiple implementation runs, you can select any completed implementation run to open the
implemented design.
在 "流程导航器 "中打开已实现的设计时，Vivado IDE 会打开已实现的网表，并针对已实现的部件应用实现、放置和布线过程中使用的物理和时序约束结果。已实现设计的放置逻辑和布线连接将加载到内存中，您可以根据需要分析和修改这些元素，以完成设计。您可以保存对约束文件、网表、实现结果和设计配置的更新。由于 Vivado IDE 允许多次实现运行，因此您可以选择任何已完成的实现运行来打开实现的设计。
In an implemented design, you can perform many design tasks, including timing analysis, power analysis, and generation of utilization statistics, which can help you determine if your design converged on desired performance targets. You can explore the design in a variety of ways using the windows in the Vivado IDE. Selected objects are always cross-selected in all related
windows. You can cross probe to lines in the source RTL files from various windows, including the Messages, Schematic, Device, Package, and Find windows. The Schematic window allows
在已实现的设计中，您可以执行许多设计任务，包括时序分析、功耗分析和生成利用率统计，这可以帮助您确定您的设计是否收敛到所需的性能目标。您可以使用 Vivado IDE 中的窗口以多种方式探索设计。在所有相关窗口中，所选对象总是交叉选择。窗口中交叉选择。您可以从各种窗口（包括 “信息”、“原理图”、“器件”、"封装 "和 "查找 "窗口）交叉探测 RTL 源文件中的行。原理图窗口允许您可以交互式地探索逻辑互连和层次结构。您还可以应用时序约束并执行进一步的时序分析。此外，您还可以交互式地应用平面规划或设计配置约束，并为将来的运行保存约束。有关详细信息，请参阅《Vivado 设计套件用户指南》： 设计分析和封闭技术 (UG906)。
you to interactively explore the logic interconnect and hierarchy. You can also apply timing constraints and perform further timing analysis. In addition, you can interactively apply floorplanning or design configuration constraints and save the constraints for future runs. For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

In the Device window, you can explore the placement or the routing results by toggling the Routing Resources button . As you zoom, the amount of detail shown in the Device window increases. You can interactively alter placement and routing as well as design configuration, such as look-up table (LUT) equations and random access memory (RAM) initialization. You can also select results in the Device or Schematic windows to cross probe back to problem lines in the RTL files. In the Schematic window, you can interactively explore the logic interconnect and hierarchy. For more information, see the Vivado Design Suite User Guide: Design Analysis and
Closure Techniques (UG906).
在 "设备 "窗口中，您可以通过切换 "布线资源 "按钮来查看布局或布线结果。随着缩放，"器件 "窗口中显示的细节量也会增加。您可以交互式更改布局和布线以及设计配置，如查找表 (LUT) 公式和随机存取存储器 (RAM) 初始化。您还可以选择 "器件 "或 "原理图 "窗口中的结果，以交叉探测 RTL 文件中的问题行。在原理图窗口中，您可以交互式地探索逻辑互连和层次结构。更多信息，请参阅《Vivado 设计套件用户指南》： 设计分析和封闭技术 (UG906)。

To open an implemented design, use one of the following methods:
• In the Implementation section of the Flow Navigator, click Open Implemented Design.
• Select Flow → Open Implemented Design.
• In the Design Runs view, double-click the run name.
要打开已实现的设计，请使用以下方法之一：

• 在 "流程导航器 "的 "实现 "部分，单击 “打开已实现的设计”。
• 选择流程 → 打开已实现设计。
• 在 "设计运行 "视图中，双击运行名称。

TIP: Because the Flow Navigator reflects the state of the active run, the Open Implemented Design command might be disabled or greyed out if the active run is not implemented. In this case, use the Implementation popup menu in the Flow Navigator to open an implemented design from any of the
completed implementation runs.提示：由于流程导航器反映的是活动运行的状态，如果活动运行未执行，则 "打开已执行设计 "命令可能被禁用或显示为灰色。在这种情况下，请使用流程导航器中的 "实现 "弹出菜单，从任何已完成的实现运行中打开已实现的设计。

The following figure shows the default layout view for an open implemented design.下图显示了打开的已实现设计的默认布局视图

Note: The Device window might display placement only or routing depending on the state the window was in when it was last closed. In the Device window, click the Routing Resources button to toggle the view to display only placement or routing.注："设备 "窗口可能只显示布局或布线，具体取决于上次关闭窗口时的状态。在 "设备 "窗口中，单击 "布线资源 "按钮可切换视图，使其仅显示布局或布线。

Updating Out-of-Date Designs

During the design process, source files or constraints often require modification. The Vivado IDE manages the dependencies of these files and indicates when the design data in the current design is out of date. For example, changing settings, such as the target part or active constraint
set, can make a design out of date.
As source files, netlists, or implementation results are updated, an out-of-date message is displayed in the design window banner of an open synthesized or implemented design to indicate that the run is out of date (shown in the following figure). Click the associated more info link to view which aspects of the design are out of date.

在设计过程中，源文件或约束经常需要修改。Vivado IDE 会管理这些文件的依赖关系，并在当前设计中的设计数据过时时发出提示。例如，更改目标器件或活动约束集等设置会使设计过时。
随着源文件、网表或实现结果的更新，在打开的综合或实现设计的设计窗口横幅中会显示一条过时信息，以指示运行已过时（如下图所示）。单击相关的更多信息链接，查看设计的哪些方面已过期。

From the design window banner, use any of the following actions to resolve an out-of-date design:
在设计窗口横幅上，使用以下任一操作来解决设计过时的问题：
• Click More Info, and click the Force up-to-date link in the Out-of-Date Due to window that appears.

• 单击 “更多信息”，然后在出现的 "由于过时 "窗口中单击 "强制更新 "链接。

Force up-to-date resets the NEEDS_REFRESH property on the active synthesis or implementation runs as needed to force the runs into an up-to-date state. The associated Tcl command is shown in the following sample code:
强制更新会根据需要重置活动综合或实现运行的 NEEDS_REFRESH 属性，以强制运行进入最新状态。相关的 Tcl 命令如以下示例代码所示：
set_property NEEDS_REFRESH false [get_runs synth_2]

Note: Use this command to force designs up to date when a minor design change was made, and you do not want to refresh the design.
注意：当设计发生微小更改，而您又不想刷新设计时，可使用此命令强制更新设计。

• Click Reload to refresh the in-memory view of the current design, eliminating any unsaved changes you made to the design data.
• Click Close Design to close the out-of-date design.

• 单击重新加载（Reload）刷新当前设计的内存视图，消除对设计数据所做的任何未保存更改。
• 单击关闭设计关闭过时的设计。

Using View Layouts to Perform Design Tasks
使用视图布局执行设计任务

When a design is open, several default view layouts (shown in the following figure) are provided to enable you to more easily work on specific design tasks, such as I/O planning, floorplanning, and debug configuration. Changing view layouts simply alters the windows that are displayed,
which enables you to focus on a particular design task. You can also create custom view layouts using the Save Layout As command.
当设计打开时，会提供几种默认视图布局（如下图所示），使您能更轻松地完成特定的设计任务，如 I/O 规划、平面规划和调试配置。更改视图布局只需改变显示的窗口、这样您就能专注于特定的设计任务。您还可以使用 "布局另存为 "命令创建自定义视图布局。

Note: Default view layouts are available only when a design is open.
注意：默认视图布局仅在设计打开时可用。

Saving Design Changes

In the Vivado IDE, you interactively edit the active design in memory. It is important to save the design when you make changes to constraints, netlists, and design parameters, such as power analysis characteristics, hardware configuration mode parameters, and debug configuration. For changes made while interactively editing an open design, you can save the changes either back to your original XDC constraint files or to a new constraint set as described in the following sections.
在 Vivado IDE 中，您可以交互式编辑内存中的活动设计。对约束、网表和设计参数（如功率分析特性、硬件配置模式参数和调试配置）进行更改时，保存设计非常重要。对于在交互编辑打开的设计时所作的更改，您可以将更改保存回原始 XDC 约束文件，或保存到新的约束集，如下文所述。

Saving Changes to Original XDC Constraint Files
保存对原始 XDC 约束文件的更改

To save any changes you made to your design data back to your original XDC constraint files,select File → Constraints → Save, or click the Save Constraints button .
要将对设计数据所做的任何更改保存回原始 XDC 约束文件，请选择文件 → 约束 → 保存，或单击保存约束按钮。

The Save Constraints command saves any changes made to the constraints, debug cores and configuration, and design configuration settings made in the open design. The Vivado IDE attempts to maintain the original file format as much as possible. Additional constraints are added at the end of the file. Changes to existing constraints remain in their original file locations.
保存约束命令可保存在开放设计中对约束、调试核和配置以及设计配置设置所做的任何更改。Vivado IDE 会尽量保持原始文件格式。附加约束会添加到文件末尾。对现有约束的更改保留在其原始文件位置。

Saving Changes to a New Constraint Set
将更改保存到新约束集

To save changes to the design to a new constraint set, select File → Constraints → Save As to create a new constraint file.
要将对设计的更改保存到新的约束集，请选择文件 → 约束 → 另存为以创建新的约束文件。

This saves any changes while preserving your original constraints source files. The new constraint set includes all design constraints, including all changes. This is one way to maintain your original XDC source files. You can also make the new constraint set the active constraint set, so that it is
automatically applied to the next run or when opening designs.
这将保存任何更改，同时保留原始约束源文件。新约束集包含所有设计约束，包括所有更改。这是保留原始 XDC 源文件的一种方法。您还可以将新约束集设置为活动约束集，这样它就会自动应用于下一次运行或打开设计。

Closing Designs

You can close designs to reduce the number of designs in memory and to prevent multiple locations where sources can be edited. In some cases, you are prompted to close a design prior to changing to another design representation. To close individual designs, do either of the following:
• In the design title bar, click the close button (X).
• In the Flow Navigator, right-click the design, and select Close.
可以关闭设计来减少内存中的设计数量，并防止在多个位置编辑源。在某些情况下，系统会提示您在切换到另一个设计表示之前关闭一个设计。要关闭单个设计，请执行以下操作之一：

• 在设计标题栏中，单击关闭按钮 (X)。
• 在流程导航器中，右键单击设计，然后选择关闭

Analyzing Implementation Results

When you open an implemented design, placement and routing results are displayed in the Device window. In the Timing Results window, you can select timing paths to highlight the placement and routing for the selected path in the Device window. You can also interactively edit placement and routing to achieve design goals and change design characteristics, such as LUT equations, RAM initialization, and phase-locked loop (PLL) configuration. For more information,see the Vivado Design Suite User Guide: Implementation (UG904).
打开已实现的设计时，布局和布线结果会显示在 "设备 "窗口中。在 "时序结果 "窗口中，您可以选择时序路径，以在 "器件 "窗口中突出显示所选路径的布局和布线。您还可以交互式编辑布局和布线，以实现设计目标和更改设计特性，如 LUT 方程、RAM 初始化和锁相环 (PLL) 配置。有关更多信息，请参阅《Vivado 设计套件用户指南》： 实现 (UG904)。

IMPORTANT! Changes are made on the in-memory version of the implemented design only. Resetting the run causes changes to be lost. To save the changes, use the Save Checkpoint command, as described in
Saving Design Changes to Design Checkpoints.
重要！仅对内存版本的已执行设计进行更改。重置运行会导致更改丢失。要保存更改，请使用保存检查点命令，如在《将设计变更保存到设计检查点》中所述。

Related Information
Saving Design Changes to Design Checkpoints

Running Timing Analysis

The Vivado IDE provides a graphical way to configure and view timing analysis results. You can experiment with various types of timing analysis parameters using Tools → Timing commands.You can use the Clock Networks and Clock Interaction report windows to view clock topology
and relationships. You can also use the Slack Histogram window to see an overall view of the design timing performance. For more information, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
Vivado IDE 提供了一种配置和查看时序分析结果的图形方式。您可以使用工具 → 时序命令尝试使用各种类型的时序分析参数和关系。您还可以使用 Slack Histogram 窗口查看设计时序性能的整体情况。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接： 设计分析和封闭技术 (UG906) 中的链接。

In addition, the Vivado IDE has many timing analysis options available through the Tcl Console and SDC constraint options. Many standard report Tcl commands are available to provide information about the clock structure, logic relationships, and constraints applied to your design.
此外，Vivado IDE 还可通过 Tcl 控制台和 SDC 约束选项提供许多时序分析选项。许多标准报告 Tcl 命令可用来提供有关时钟结构、逻辑关系和应用于设计的约束的信息。

For more information, see the Vivado Design Suite Tcl Command Reference Guide (UG835), or type help report_*.

Running Reports: DRC, Power, Utilization Analysis

The Vivado IDE provides a graphical way to configure and view power, utilization, and DRC analysis results. The report_power command lets you experiment with power parameters and quickly estimate power at any stage of the design. The report_utilization command lets you analyze the utilization statistics of various types of device resources. The report_design_analysis command lets you analyze critical path characteristics and the complexity of the design to help identify and analyze problem areas that are prone to routing congestion and timing closure issues. The report_drc command let you configure and run a comprehensive set of DRCs to identify problems that must be solved prior to generating the bitstream for the design.
Vivado IDE 提供了一种图形方式来配置和查看功耗、利用率和 DRC 分析结果。通过 report_power 命令，您可以尝试使用功耗参数，并在设计的任何阶段快速估算功耗。使用 report_utilization 命令可以分析各类器件资源的利用率统计。通过 report_design_analysis 命令，可以分析关键路径特性和设计的复杂性，帮助识别和分析容易出现布线拥塞和时序闭合问题的区域。report_drc 命令可让您配置和运行一组全面的 DRC，以确定在生成设计的比特流之前必须解决的问题。

In the Vivado IDE, report results are provided with links to select problem areas or offending objects. In addition, many reports can write an RPX file to save the report results in an interactive report file that can be reloaded into memory, with links to design objects. Reloading the report reconnects the object links so that cross-selection between the report in the Vivado IDE and the design is enabled. For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906), or refer to the report_xxx commands in the Vivado Design Suite Tcl Command Reference Guide (UG835).
在 Vivado IDE 中，报告结果提供了选择问题区域或违规对象的链接。此外，许多报告还可以编写 RPX 文件，将报告结果保存在可重新加载到内存的交互式报告文件中，并提供设计对象链接。重新加载报告可重新连接对象链接，从而启用 Vivado IDE 中报告与设计之间的交叉选择。有关更多信息，请参阅《Vivado 设计套件用户指南》： 设计分析和封闭技术》(UG906) 或参阅《Vivado Design Suite Tcl 命令参考指南》(UG835) 中的 report_xxx 命令。

Report strategies enable you to define groups of reports and associate all the reports with a particular run. Report strategies can be created by using Tools→Settings→Strategies→Report Strategies. Individual reports can be specified for each step of a run. Report strategy is a property of a run. Setting report strategy on the run generates all specified reports when the run is launched.
通过报告策略，可以定义报告组，并将所有报告与特定运行关联起来。可以使用工具→设置→策略→报告策略创建报告策略。可以为运行的每个步骤指定单独的报告。报告策略是运行的一个属性。在运行上设置报告策略后，运行启动时将生成所有指定的报告。

11、Device Programming, Hardware Verification,and Debugging（设备编程、硬件验证和调试）

In the Vivado IDE, the Vivado logic analyzer includes many features to enable verification anddebugging of the design. You can configure and implement IP debug cores, such as the Integrated Logic Analyzer (ILA) and Debug Hub core, in either an RTL or synthesized netlist. Opening the
synthesized or implemented design in the Vivado IDE enables you to select and configure the required probe signals into the cores. You can launch the Vivado logic analyzer on any run that has a completed bitstream file for performing interactive hardware verification. In addition, you can create programming bitstream files for any completed implementation run. Bitstream file generation options are configurable. Launch the Vivado device programmer to configure and program the part. You can launch the Vivado logic analyzer directly from the Vivado IDE for further analysis of the routing or device resources. For more information, see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).
在 Vivado IDE 中，Vivado 逻辑分析器包含许多功能，用于验证和调试设计。您可以在 RTL 或合成网表中配置和实现 IP 调试核，如集成逻辑分析器 (ILA) 和调试集线器核。在 Vivado IDE 中打开已综合或已实现的设计，就可以选择和配置到核中所需的探针信号。您可以在任何已完成位流文件的运行上启动 Vivado 逻辑分析器，以执行交互式硬件验证。此外，您还可以为任何已完成的实现运行创建编程位流文件。位流文件生成选项是可配置的。启动 Vivado 器件编程器对器件进行配置和编程。您可以直接从 Vivado IDE 启动 Vivado 逻辑分析器，以进一步分析路由或器件资源。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接： 编程和调试 (UG908) 中的链接。

Implementing Engineering Changes (ECOs) for Debugging
为调试而实施工程变更（ECO）

Engineering change orders (ECOs) are modifications to an implemented design. The Vivado Design Suite provides an ECO flow that lets you implement changes to an existing design checkpoint (DCP) and generate updated bitstream files. After implementing an ECO on the design, you might also need to modify, add, or delete debug cores or probes to the implemented design. Refer to this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908) for information on the debug ECO flow.
工程变更单 (ECO) 是对已实现设计的修改。Vivado 设计套件提供的 ECO 流程可让您对现有设计检查点 (DCP) 实施更改并生成更新的比特流文件。在设计上实施 ECO 后，您可能还需要修改、添加或删除已实施设计的调试核或探针。请参阅《Vivado 设计套件用户指南》中的此链接： 编程和调试 (UG908) 中的链接，了解有关调试 ECO 流程的信息。

12、Using Project Mode Tcl Commands（使用工程模式 tcl 命令）

The following table shows the basic Project Mode Tcl commands that control project creation, implementation, and reporting. For details on each command, see the Vivado Design Suite Tcl Command Reference Guide (UG835).下表列出了控制项目创建、实施和报告的基本项目模式 Tcl 命令。有关各命令的详细信息，请参阅《Vivado Design Suite Tcl 命令参考指南》(UG835)。

TIP: The best way to understand the Tcl commands involved in a design task is to run the command in the Vivado IDE and inspect the syntax in the Tcl Console or the vivado.jou file.提示：了解设计任务中涉及的 Tcl 命令的最佳方法是在 Vivado IDE 中运行该命令，并检查 Tcl 控制台或 vivado.jou 文件中的语法。

Table 3: Basic Project Mode Tcl Commands

create_project
Creates the Vivado Design Suite project. Arguments include project name and location, design top module name, and target part.创建 Vivado Design Suite 项目。参数包括项目名称和位置、设计顶层模块名称和目标器件。

add_files
Adds source files to the project. These include Verilog (.v), VHDL (.vhd or .vhdl), SystemVerilog(.sv), IP and System Generator modules (.xco or .xci), IP integrator subsystems (.bd), and XDC constraints (.xdc or .sdc).
Individual files can be added, or entire directory trees can be scanned for legal sources and automatically added to the project.
向项目添加源文件。这些文件包括 Verilog (.v) 、VHDL (.vhd 或 .vhdl)、SystemVerilog(.sv)、IP 和系统发生器模块 (.xco 或 .xci)、IP 集成子系统 (.bd) 和 XDC 约束 (.xdc 或 .sdc)。可以添加单个文件，也可以扫描整个目录树，查找合法来源并自动添加到项目中。
Note: The .xco file is no longer supported in UltraScale device designs.
注意：UltraScale 器件设计不再支持 .xco 文件。

set_property
Used for multiple purposes in the Vivado Design Suite. For projects, it can be used to define VHDL libraries for sources, simulation-only sources, target constraints files, tool settings, and so forth.在 Vivado 设计套件中有多种用途。对于项目，它可用于定义源的 VHDL 库、仿真专用源、目标约束文件、工具设置等。

import_files
Imports the specified files into the current file set, effectively adding them into the project infrastructure. It is also used to assign XDC files into constraints sets.将指定文件导入当前文件集，有效地将其添加到项目基础结构中。它还用于将 XDC 文件分配到约束集。

launch_runs
launch_runs -to_step
Starts either synthesis or implementation and bitstream generation. This command encompasses the individual implementation commands as well as the standard reports generated after the run completes. It is used to launch all of the steps of the synthesis or implementation process in a single command, and to track the tools progress through that process. The -to_step option is used to launch the implementation process, including bitstream generation, in incremental steps.开始综合或执行以及位流生成。该命令包括单个执行命令以及运行完成后生成的标准报告。它用于在一条命令中启动综合或实现过程的所有步骤，并跟踪工具在该过程中的进展。-to_step选项用于以递增步骤启动实现过程，包括比特流生成。

wait_on_run
Ensures the run is complete before processing the next commands in a Tcl script.在处理 Tcl 脚本中的下一条命令之前，确保运行已完成。

open_run
Opens either the synthesized design or implemented design for reporting and analysis. A design must be opened before information can be queried using Tcl for reports, analysis, and so forth.打开合成的设计或实现的设计，以便进行报告和分析。在使用 Tcl 进行报告、分析等信息查询之前，必须先打开设计。

close_design Closes the in-memory design.关闭内存设计。

start_gui
stop_gui
Opens or closes the Vivado IDE with the current design in memory.
以内存中的当前设计打开或关闭 Vivado IDE。

Note: This document is not a complete reference for the available Tcl commands. Instead, see the Vivado Design Suite Tcl Command Reference Guide (UG835).
注意：本文档并非可用 Tcl 命令的完整参考资料。请参阅《Vivado Design Suite Tcl 命令参考指南》(UG835)。

Project Mode Tcl Script Examples

The following examples show a Tcl script for an RTL project and a netlist project. The first example script, run_bft_kintex7_project.tcl, is available in the Vivado Design Suite
installation at:
以下示例展示了 RTL 项目和网表项目的 Tcl 脚本。第一个示例脚本 run_bft_kintex7_project.tcl 在 Vivado 设计套件安装包中提供，安装地址为
安装包中，网址为

<install_dir>/Vivado/2020.2/examples/Vivado_Tutorial

You can source these scripts from the Vivado Tcl shell, or the Tcl Console inside of the Vivado IDE.
您可以从 Vivado Tcl 外壳或 Vivado IDE 内的 Tcl 控制台获取这些脚本。

RTL Project Tcl Script

#   run_bft_kintex7_project.tcl
# BFT sample design
#
# NOTE: Typical usage would be "vivado -mode tcl -source
run_bft_kintex7_project.tcl"
# To use -mode batch comment out the "start_gui" and "open_run impl_1" to
save time
#
create_project project_bft ./Tutorial_Created_Data/project_bft -part
xc7k70tfbg484-2
add_files {./Sources/hdl/FifoBuffer.v ./Sources/hdl/async_fifo.v ./
Sources/hdl/bft.vhdl}
add_files -fileset sim_1 ./Sources/hdl/bft_tb.v
add_files ./Sources/hdl/bftLib
set_property library bftLib [get_files {./Sources/hdl/bftLib/round_4.vhdl \
./Sources/hdl/bftLib/round_3.vhdl ./Sources/hdl/bftLib/round_2.vhdl ./
Sources/hdl/bftLib/round_1.vhdl \
./Sources/hdl/bftLib/core_transform.vhdl ./Sources/hdl/bftLib/
bft_package.vhdl}]
import_files -force
import_files -fileset constrs_1 -force -norecurse ./Sources/
bft_full_kintex7.xdc
# Mimic GUI behavior of automatically setting top and file compile order
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
# Launch Synthesis
launch_runs synth_1
wait_on_run synth_1
open_run synth_1 -name netlist_1
# Generate a timing and power reports and write to disk
report_timing_summary -delay_type max -report_unconstrained -
check_timing_verbose \
-max_paths 10 -input_pins -file ./Tutorial_Created_Data/project_bft/
syn_timing.rpt
report_power -file ./Tutorial_Created_Data/project_bft/syn_power.rpt
# Launch Implementation
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
# Generate a timing and power reports and write to disk
# comment out the open_run for batch mode
open_run impl_1
report_timing_summary -delay_type min_max -report_unconstrained -
check_timing_verbose \
-max_paths 10 -input_pins -file ./Tutorial_Created_Data/project_bft/
imp_timing.rpt
report_power -file ./Tutorial_Created_Data/project_bft/imp_power.rpt
# comment out the for batch mode
start_gui
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Netlist Project Tcl Script

# Kintex-7 Netlist Example Design
#
# STEP#1: Create Netlist Project, add EDIF sources, and add constraints
#
create_project -force project_K7_netlist ./Tutorial_Created_Data/
project_K7_netlist/ -part xc7k70tfbg676-2
# Property required to define Netlist project
set_property design_mode GateLvl [current_fileset]
add_files {./Sources/netlist/top.edif}
import_files -force
import_files -fileset constrs_1 -force ./Sources/top_full.xdc
#
# STEP#2: Configure and Implementation, write bitstream, and generate
reports
#
launch_runs impl_1
wait_on_run impl_1
launch_runs impl_1 -to_step write_bitstream
wait_on_run impl_1
open_run impl_1
report_timing_summary -delay_type min_max -report_unconstrained -
check_timing_verbose \
-max_paths 10 -input_pins -file ./Tutorial_Created_Data/project_K7_netlist/
imp_timing.rpt
report_power -file ./Tutorial_Created_Data/project_K7_netlist/imp_power.rpt
#
# STEP#3: Start IDE for design analysis
#
start_gui
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四、Using Non-Project Mode（非工程模式）

This chapter highlights the differences between Non-Project Mode and Project Mode. To fully understand Non-Project Mode in the AMD Vivado™ Design Suite, you should be familiar with Project Mode as described in Using Project Mode.本章重点介绍非项目模式和项目模式之间的区别。要充分理解 AMD Vivado™ 设计套件中的非项目模式，您应熟悉项目模式（如 "使用项目模式 "中所述）。

In Non-Project Mode, you use Tcl commands to compile a design through the entire flow. In this mode, an in-memory project is created to let the AMD Vivado™ tools manage various properties of a design, but the project file is not written to disk, and the project status is not preserved.在非项目模式下，您可以使用 Tcl 命令在整个流程中编译设计。在此模式下，会创建一个内存项目，以便 AMD Vivado™ 工具管理设计的各种属性，但项目文件不会写入磁盘，项目状态也不会保留。

TIP: An in-memory project is also generated in Non-Project Mode for the Vivado tool to use. However, it is not preserved as part of the design.提示：在非项目模式下也会生成一个内存项目供 Vivado 工具使用。但是，它不会作为设计的一部分保存。

Tcl commands provide the flexibility and power to set up and run your designs and perform analysis and debugging. Tcl commands can be run in batch mode, from the Vivado Design Suite Tcl shell, or through the Vivado IDE Tcl Console. Non-Project Mode enables you to have full
control over each design flow step, but you must manually manage source files, reports, and intermediate results known as design checkpoints. You can generate a variety of reports, perform DRCs, and write design checkpoints at any stage of the implementation process.
Tcl 命令为设置和运行设计以及执行分析和调试提供了灵活性和强大功能。Tcl 命令可以批处理模式、Vivado Design Suite Tcl 外壳或 Vivado IDE Tcl 控制台运行。非项目模式使您能够完全控制每个设计流程步骤，但您必须手动管理源文件、报告和称为设计检查点的中间结果。您可以在实现过程的任何阶段生成各种报告、执行 DRC 和编写设计检查点。

Unlike Project Mode, Non-Project Mode does not include features such as runs infrastructure, source file management, or design state reporting. Each time a source file is updated, you must rerun the design manually. Default reports and intermediate files are not created automatically in this mode. However, you can create a wide variety of reports and design checkpoints as needed using Tcl commands. In addition, you can still access the GUI-based design analysis and constraints assignment features of the Vivado IDE. You can open either the current design in memory or any saved design checkpoint in the Vivado IDE.
与项目模式不同，非项目模式不包括运行基础结构、源文件管理或设计状态报告等功能。每次更新源文件时，都必须手动重新运行设计。在该模式下，不会自动创建默认报告和中间文件。不过，您可以根据需要使用 Tcl 命令创建各种报告和设计检查点。此外，您仍然可以访问 Vivado IDE 基于图形用户界面的设计分析和约束分配功能。您可以在 Vivado IDE 中打开内存中的当前设计或任何已保存的设计检查点。

When you launch the Vivado IDE in Non-Project Mode, the Vivado IDE does not include Project Mode features such as the Flow Navigator, Project Summary, or Vivado IP catalog. In Non-Project Mode, you cannot access or modify synthesis or implementation runs in the Vivado IDE.However, if the design source files reside in their original locations, you can cross probe to design objects in the different windows of the Vivado IDE. For example, you can select design objects and then use the Go To Instantiation, Go To Definition, or Go To Source commands to open the associated RTL source file and highlight the appropriate line.
在非项目模式下启动 Vivado IDE 时，Vivado IDE 不包含项目模式功能，例如流程导航器、项目摘要或 Vivado IP 目录。在非项目模式下，您无法访问或修改 Vivado IDE 中的综合或实现运行。但是，如果设计源文件位于其原始位置，您可以交叉探测 Vivado IDE 不同窗口中的设计对象。例如，您可以选择设计对象，然后使用转到实例、转到定义或转到源代码命令打开相关的 RTL 源文件并高亮显示相应的行。

IMPORTANT! Some of the features of Project Mode, such as source file and run results management,saving design and tool configuration, design status, and IP integration, are not available in Non-Project Mode.重要！项目模式的某些功能，如源文件和运行结果管理、保存设计和工具配置、设计状态和 IP 集成，在非项目模式下不可用。

You must write reports or design checkpoints to save the in-memory design as it progresses. The design checkpoint (DCP) refers to a file that is an exact representation of the in-memory design.You can save a design checkpoint after each step in the design flow, such as post synthesis, post optimization, post placement. The DCP file can be read back into the Vivado Design Suite to restore the design to the state captured in the checkpoint file.您必须编写报告或设计检查点，以便在设计过程中保存内存设计。设计检查点 (DCP) 指的是精确表示内存中设计的文件。您可以在设计流程中的每个步骤（如综合后、优化后、放置后）后保存设计检查点。可以将 DCP 文件读回 Vivado 设计套件，将设计恢复到检查点文件中捕获的状态。

You can also open a DCP in the Vivado IDE to perform interactive constraints assignment and design analysis. Because you are viewing the active design in memory, any changes are automatically passed forward in the flow. You can also save updates to new constraint files or design checkpoints for future runs.您还可以在 Vivado IDE 中打开 DCP，以执行交互式约束分配和设计分析。由于您是在内存中查看活动设计，因此任何更改都会自动在流程中向前传递。您还可以将更新保存到新的约束文件或设计检查点，以便将来运行。

While most Non-Project Mode features are also available in Project Mode, some Project Mode features are not available in Non-Project Mode. These features include source file and run results management, saving design and tool configuration, design status, and IP integration. On the other hand, you can use Non-Project mode to skip certain processes, thereby reducing the
memory footprint of the design, and saving disk space related to projects.
虽然大多数非项目模式功能在项目模式下也可用，但有些项目模式功能在非项目模式下不可用。这些功能包括源文件和运行结果管理、保存设计和工具配置、设计状态和 IP 集成。另一方面，您可以使用非项目模式跳过某些流程，从而减少设计的内存占用，并节省时间。另一方面，您可以使用非项目模式跳过某些进程，从而减少设计的内存占用，并节省与项目相关的磁盘空间。

Related Information Using Project Mode

1、Non-Project Mode Advantages（非工程模式的优势）

Non-Project Mode enables you to have full control over each design flow step. You can take advantage of a compile-style design flow.非项目模式使您可以完全控制每个设计流程步骤。您可以利用编译风格的设计流程。

In this mode, you manage your design manually, including:
• Manage HDL Source files, constraints, and IP
• Manage dependencies
• Generate and store synthesis and implementation results
在此模式下，您可以手动管理设计，包括

• 管理 HDL 源文件、约束和 IP
• 管理依赖关系
• 生成并存储综合和实现结果

The Vivado Design Suite includes an entire suite of Vivado Tcl commands to create, configure,implement, analyze, and manage designs as well as IP. In Non-Project Mode, you can use Tcl commands to do the following:
• Compile a design through the entire flow
• Analyze the design and generate reports
Vivado 设计套件包括一整套 Vivado Tcl 命令，用于创建、配置、实现、分析和管理设计以及 IP。在非项目模式下，您可以使用 Tcl 命令执行以下操作：

• 通过整个流程编译设计
• 分析设计并生成报告

2、Reading Design Sources（读取设计文件）

When using Non-Project Mode, the various design sources are read into the in-memory design for processing by the implementation tools. Each type of Vivado Design Suite source file has a read_* Tcl command to read the files, such as read_verilog, read_vhdl, read_ip, read_edif, or read_xdc. Sources must be read each time the Tcl script or interactive flow is started.
使用 "非项目模式 "时，各种设计源将被读入内存中的设计，供实现工具处理。每种类型的 Vivado Design Suite 源文件都有一个 read_ Tcl 命令来读取文件，如 read_verilog、read_vhdl、read_ip、read_edif 或 read_xdc。每次启动 Tcl 脚本或交互式流程时都必须读取源文件。*

TIP: Because there is no project structure to add the files or import the files into, you should not use the add_files or import_files Tcl commands to add files to a non-project based design.提示：由于没有项目结构来添加文件或导入文件，因此不应使用 add_files 或 import_files Tcl 命令来为非基于项目的设计添加文件。

Managing Source Files

In Non-Project Mode, you manage source files manually by reading the files into the in-memory design in a specific order. This gives you full control over how to manage the files and where files are located. Sources can be read from any network accessible location. Sources with read-only permissions are processed accordingly.在非项目模式下，您可以按照特定顺序将文件读入内存设计，从而手动管理源文件。这样就可以完全控制如何管理文件以及文件的位置。源文件可以从任何网络可访问位置读取。具有只读权限的源文件将被相应处理。

Working with a Revision Control System

Many design teams use source management systems to store various design configurations and revisions. There are multiple commercially available systems, such as Revision Control System (RCS), Concurrent Versions System (CVS), Subversion (SVN), ClearCase, Perforce, Git, BitKeeper,and many others. The Vivado tools can interact with all such systems. The Vivado Design Suite uses and produces files throughout the design flow that you may want to manage under revision control.
许多设计团队使用源代码管理系统来存储各种设计配置和修订。市场上有多种可用的系统，如修订控制系统 (RCS)、并发版本系统 (CVS)、Subversion (SVN)、ClearCase、Perforce、Git、BitKeeper 等。Vivado 工具可与所有这些系统交互。Vivado 设计套件在整个设计流程中使用并生成文件，您可能希望在修订控制下管理这些文件。

Working with revision control software is simple when using the Non-Project mode. The designer checks out the needed source files into a local directory structure. The sources are then instantiated into a top-level design to create the design. New source files might also need to be created and read into the design using various read_* Tcl commands. The design files are passed to the Vivado synthesis and implementation tools. However, the source files remain in their original locations. The checked-out sources can be modified interactively, or with Tcl commands during the design session using appropriate code editors. Source files are then checked back into the source control system as needed. Design results, such as design checkpoints, analysis reports, and bitstream files, can also be checked in for revision
management. For more information on working with revision control software, see Chapter 5: Source Management and Revision Control Recommendations.
使用非项目模式时，修订控制软件的操作非常简单。设计人员将所需的源文件检出到本地目录结构中。然后将源文件实例化到顶层设计中，创建设计。可能还需要创建新的源文件，并使用各种 read_* Tcl 命令将其读入设计。设计文件将传递给 Vivado 综合和实现工具。但是，源文件仍保留在其原始位置。在设计会话期间，可使用适当的代码编辑器以交互方式或 Tcl 命令修改签出的源文件。然后根据需要将源文件检回到源控制系统中。设计结果，如设计检查点、分析报告和比特流文件，也可签入进行修订管理。有关使用修订控制软件的更多信息，请参阅第 5 章：源代码管理和修订控制建议。

VIDEO: For information on best practices when using revision control systems with the Vivado tools, see the Vivado Design Suite QuickTake Video: Using Vivado Design Suite with Revision Control.视频： 有关在 Vivado 工具中使用修订控制系统的最佳实践的信息，请参阅 Vivado Design Suite QuickTake 视频： 将 Vivado Design Suite 与版本控制系统结合使用。

Using Third-Party Synthesized Netlists

The Vivado Design Suite supports implementation of synthesized netlists, such as when using a third-party synthesis tool. The external synthesis tool generates a Verilog or EDIF netlist and a constraints file, if applicable. These netlists can be used standalone or mixed with RTL files in either Project Mode or Non-Project Mode.
Vivado 设计套件支持综合网表的实现，例如在使用第三方综合工具时。外部综合工具会生成 Verilog 或 EDIF 网表和约束文件（如适用）。这些网表可以单独使用，也可以在项目模式或非项目模式下与 RTL 文件混合使用。

3、Working with IP and IP Subsystems

In Non-Project Mode, output products must be generated for the IP or block designs prior to launching the top-level synthesis. You can configure IP to use RTL sources and constraints, or use the OOC netlist from a synthesized design checkpoint as the source in the top-level design. The default behavior is to generate an OOC design checkpoint for each IP.在非项目模式下，必须在启动顶层综合之前为 IP 或块设计生成输出产品。您可以将 IP 配置为使用 RTL 源和约束，或使用合成设计检查点的 OOC 网表作为顶层设计的源。默认行为是为每个 IP 生成一个 OOC 设计检查点。

In Non-Project Mode, you can add IP to your design using any of the following methods:
在非项目模式下，您可以使用以下任一方法将 IP 添加到设计中：
• IP generated using the Vivado IP catalog (.xci format or .xcix format for core container)- 使用 Vivado IP 目录生成的 IP（核心容器为 .xci 格式或 .xcix 格式）
If the out-of-context design checkpoint file exists in the IP directory, it is used for implementation and a black box is inserted for synthesis. If a design checkpoint file does not exist in the IP directory, the RTL and constraints sources are used for global synthesis and implementation.
如果 IP 目录中存在上下文外设计检查点文件，则使用该文件进行实现，并插入黑盒进行综合。如果 IP 目录中不存在设计检查点文件，则使用 RTL 和约束源进行全局综合和实现。
• Use Tcl commands to configure and generate the IP or block design.
Using Tcl ensures that the IP is configured, generated, and synthesized with each run.- 使用 Tcl 命令配置和生成 IP 或块设计。使用 Tcl 可确保每次运行都能配置、生成和综合 IP。

IMPORTANT! When using IP in Project Mode or Non-Project Mode, always use the XCI file not the DCP file. This ensures that IP output products are used consistently during all stages of the design flow. If the IP was synthesized out-of-context and already has an associated DCP file, the DCP file is automatically used and the IP is not re-synthesized. For more information, see this link in the Vivado Design Suite User Guide: Designing with IP (UG896).重要！在项目模式或非项目模式下使用 IP 时，应始终使用 XCI 文件而不是 DCP 文件。这可确保在设计流程的所有阶段都能一致地使用 IP 输出产品。如果 IP 是在非上下文中合成的，并且已经有相关的 DCP 文件，则会自动使用 DCP 文件，而不会重新合成 IP。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接： 使用 IP 进行设计 (UG896) 中的链接。

For more information, see this link in the Vivado Design Suite User Guide: Designing with IP (UG896), or this link in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).有关详细信息，请参阅《Vivado Design Suite 用户指南》中的此链接： 使用 IP 设计》(UG896) 中的此链接，或《Vivado Design Suite 用户指南》中的此链接： 使用 IP Integrator 设计 IP 子系统 (UG994) 中的链接。

4、Running Logic Simulation（运行逻辑仿真）

The Vivado simulator, integrated with the Vivado IDE, allows you to simulate the design, and view signals in the waveform viewer, and examine and debug the design as needed. The Vivado simulator is a fully integrated mixed-mode simulator with analog waveform display capabilities.
Using the Vivado simulator, you can perform behavioral and structural simulation of designs and full timing simulation of implemented designs.
Vivado 仿真器与 Vivado IDE 集成，可让您模拟设计，在波形查看器中查看信号，并根据需要检查和调试设计。Vivado 模拟器是一个完全集成的混合模式模拟器，具有模拟波形显示功能。
使用 Vivado 仿真器，您可以对设计进行行为和结构仿真，并对已实现的设计进行全面时序仿真。

You can also use third-party simulators to write the Verilog, VHDL netlists, and SDF format files from the open design. You can launch the Mentor Graphics ModelSim and Questa simulators from the Vivado IDE. For more information, see this link in the Vivado Design Suite User Guide:
Logic Simulation (UG900).

您还可以使用第三方仿真器来编写开放设计中的 Verilog、VHDL 网表和 SDF 格式文件。您可以从 Vivado IDE 启动 Mentor Graphics ModelSim 和 Questa 仿真器。有关详细信息，请参阅《Vivado 设计套件用户指南》中的此链接：
逻辑仿真 (UG900)。

5、Running Logic Synthesis and Implementation（运行逻辑综合和实现）

In Non-Project Mode, each implementation step is launched with a configurable Tcl command, and the design is compiled in memory. The implementation steps must be run in a specific order, as shown in the Non-Project Mode Tcl Script Example. Optionally, you can run steps such as
power_opt_design or phys_opt_design as needed. Instead of run strategies, which are only supported in Project Mode, you can use various commands to control the tool behavior. For more information, see the Vivado Design Suite User Guide: Implementation (UG904).
在非项目模式下，每个实现步骤都通过可配置的 Tcl 命令启动，并在内存中编译设计。如非项目模式 Tcl 脚本示例所示，实施步骤必须按特定顺序运行。您可以选择运行以下步骤 power_opt_design 或 phys_opt_design 等步骤。您可以使用各种命令来控制工具行为，而不是仅在项目模式下支持的运行策略。有关详细信息，请参阅《Vivado 设计套件用户指南》： 实现(UG904)。

It is important to write design checkpoints after critical design steps for design analysis and constraints definition. With the exception of generating a bitstream, design checkpoints are not intended to be used as starting points to continue the design process. They are merely snapshots of the design for analysis and constraint definition.在进行设计分析和约束定义的关键设计步骤后编写设计检查点非常重要。除生成比特流外，设计检查点不能作为继续设计过程的起点。它们只是用于分析和约束定义的设计快照。

TIP: After each design step, you can launch the Vivado IDE to enable interactive graphical design analysis and constraints definition on the active design, as described in Performing Design Analysis Using the Vivado IDE.
提示：如使用 Vivado IDE 执行设计分析中所述，在每个设计步骤之后，您可以启动 Vivado IDE，以在活动设计上启用交互式图形设计分析和约束定义。

Related Information
Non-Project Mode Tcl Script Example
Performing Design Analysis Using the Vivado IDE

6、Generating Reports（生成报告）

With the exception of the vivado.log and vivado.jou reports, reports must be generated manually with a Tcl command. You can generate various reports at any point in the design process. For more information, see the Vivado Design Suite Tcl Command Reference Guide (UG835) or Vivado Design Suite User Guide: Implementation (UG904).

除 vivado.log 和 vivado.jou 报告外，其他报告都必须使用 Tcl 命令手动生成。您可以在设计过程中的任何时刻生成各种报告。有关详细信息，请参阅《Vivado Design Suite Tcl 命令参考指南》(UG835) 或《Vivado Design Suite 用户指南》： 实现 (UG904)。

7、Using Design Checkpoints

Design checkpoints enable you to take a snapshot of your design in its current state. The current netlist, constraints, and implementation results are stored in the design checkpoint. Using design checkpoints, you can:
通过设计检查点，可以对当前状态下的设计进行快照。当前的网表、约束和实现结果都存储在设计检查点中。使用设计检查点可以：
• Restore your design if needed
• Perform design analysis
• Define constraints
• Proceed with the design flow

• 必要时恢复设计
• 进行设计分析
• 定义限制条件
• 继续设计流程
  You can write design checkpoints at different points in the flow. It is important to write design checkpoints after critical design steps for design analysis and constraints definition. You can read design checkpoints to restore the design, which might be helpful for debugging issues. The design checkpoint represents a full save of the design in its current implementation state. You
  can run the design through the remainder of the flow using Tcl commands. However, you cannot add new sources to the design.
  您可以在流程的不同点写入设计检查点。在设计分析和约束定义的关键设计步骤之后写入设计检查点非常重要。您可以读取设计检查点来恢复设计，这可能有助于调试问题。设计检查点代表设计在当前实现状态下的完整保存。您可以
  可以使用 Tcl 命令在流程的剩余部分运行设计。但是，您不能向设计中添加新的源。

Note: You can also use the write_checkpoint <file_name>.dcp and read_checkpoint <file_name>.dcp Tcl commands to write and read design checkpoints. To view a checkpoint in the Vivado IDE, use the open_checkpoint <file_name>.dcp Tcl command. For more information, see the Vivado Design Suite Tcl Command Reference Guide (UG835).
注意：还可以使用 write_checkpoint <file_name>.dcp 和 read_checkpoint <file_name>.dcp Tcl 命令来写入和读取设计检查点。要在 Vivado IDE 中查看检查点，请使用 open_checkpoint <file_name>.dcp Tcl 命令。有关详细信息，请参阅《Vivado Design Suite Tcl 命令参考指南》(UG835)。

8、Performing Design Analysis Using the Vivado IDE

In Non-Project Mode, you can launch the Vivado IDE after any design step to enable interactive graphical design analysis and constraints definition on the active design.
在非项目模式下，您可以在任何设计步骤后启动 Vivado IDE，以便对活动设计进行交互式图形设计分析和约束定义。

Opening the Vivado IDE From the Active Design

When working in Non-Project Mode, use the following commands to open and close the Vivado IDE on the active design in memory:
• start_gui opens the Vivado IDE with the active design in memory.
• stop_gui closes the Vivado IDE and returns to the Vivado Design Suite Tcl shell.
在非项目模式下工作时，使用以下命令打开和关闭内存中活动设计的 Vivado IDE：

• start_gui 打开内存中活动设计的 Vivado IDE。
• stop_gui 关闭 Vivado IDE 并返回 Vivado Design Suite Tcl shell。

CAUTION! If you exit the Vivado Design Suite from the GUI, the Vivado Design Suite Tcl shell closes and does not save the design in memory. To return to the Vivado Design Suite Tcl shell with the active design intact, use the stop_gui Tcl command rather than the exit command.
注意！如果从图形用户界面退出 Vivado Design Suite，Vivado Design Suite Tcl shell 将关闭，并且不会将设计保存在内存中。要返回 Vivado Design Suite Tcl shell 并保持活动设计不变，请使用 stop_gui Tcl 命令而不是 exit 命令。

After each stage of the design process, you can open the Vivado IDE to analyze and operate on the current design in memory (shown in the following figure). In Non-Project Mode, some of the project features are not available in the Vivado IDE, such as the Flow Navigator, Project Summary, source file access and management, and runs. However, many of the analysis and
constraint modification features are available in the Tools menu.
在设计流程的每个阶段结束后，您可以打开 Vivado IDE 对内存中的当前设计进行分析和操作（如下图所示）。在非项目模式下，Vivado IDE 中不提供某些项目功能，如流程导航器、项目摘要、源文件访问和管理以及运行。但是，许多分析和"工具 "菜单中提供了许多分析和约束修改功能。

IMPORTANT! Be aware that any changes made in the Vivado IDE are made to the active design in memory and are automatically applied to downstream tools.重要！请注意，在 Vivado IDE 中进行的任何更改都会应用到内存中的活动设计，并自动应用到下游工具。

Saving Design Changes to the Active Design

Because you are actively editing the design in memory, changes are automatically passed to downstream tools for the remainder of the Vivado IDE Tcl session. This enables you to reflect the changes in the active design and to save the changes for future attempts. Select File → Export →
Export Constraints to save constraints changes for future use. You can use this command to write a new constraints file or override your original file.
由于您是在内存中主动编辑设计，因此在 Vivado IDE Tcl 会话的剩余时间内，更改会自动传递给下游工具。这使您能够在活动设计中反映更改，并保存更改以供将来尝试。选择文件 → 导出 → 导出约束
导出约束以保存约束更改供将来使用。您可以使用此命令编写新的约束文件或覆盖原始文件。

Note: When you export constraints, the write_xdc Tcl command is run. For more information, see the Vivado Design Suite Tcl Command Reference Guide (UG835).注意：导出约束时，将运行 write_xdc Tcl 命令。有关详细信息，请参阅《Vivado Design Suite Tcl 命令参考指南》(UG835)。

Opening Design Checkpoints in the Vivado IDE

You can use the Vivado IDE to analyze designs saved as design checkpoints. You can run a design in Non-Project Mode using Tcl commands (synth_design, opt_design, power_opt_design, place_design, phys_opt_design, and route_design), store the design at any stage, and read it in a Vivado IDE session. You can start with a routed design,analyze timing, adjust placement to address timing problems, and save your work for later, even if the design is not fully routed. The Vivado IDE view banner displays the open design checkpoint name.
您可以使用 Vivado IDE 分析保存为设计检查点的设计。您可以使用 Tcl 命令（synth_design、opt_design、power_opt_design、place_design、phys_opt_design 和 route_design）在非项目模式下运行设计，在任何阶段存储设计，并在 Vivado IDE 会话中读取设计。您可以从布线设计开始，分析时序，调整布局以解决时序问题，并保存您的工作以供以后使用，即使设计尚未完全布线。Vivado IDE 视图横幅显示打开的设计检查点名称。

Saving Design Changes to Design Checkpoints

You can open, analyze, and save design checkpoints. You can also save changes to a new design checkpoint:
• Select File → Checkpoint → Save to save changes made to the current design checkpoint.
• Select File → Checkpoint → Write to save the current state of the design checkpoint to a new design checkpoint.
您可以打开、分析和保存设计检查点。您还可以将更改保存到新的设计检查点：

• 选择文件 → 检查点 → 保存，保存对当前设计检查点所做的更改。
• 选择文件 → 检查点 → 写入，将设计检查点的当前状态保存到新的设计检查点。

9、Using Non-Project Mode Tcl Commands（使用非工程模式TCL命令）

The following table shows the basic Non-Project Mode Tcl commands. When using Non-Project Mode, the design is compiled using read_verilog, read_vhdl, read_edif, read_ip, read_bd, and read_xdc type commands. The sources are ordered for compilation and passed to synthesis. For information on using the Vivado Design Suite Tcl shell or using batch Tcl scripts, see Working with Tcl.下表列出了基本的非项目模式 Tcl 命令。使用非项目模式时，将使用 read_verilog、read_vhdl、read_edif、read_ip、read_bd 和 read_xdc 类型的命令编译设计。编译时对源代码进行排序，并将其传递给综合。有关使用 Vivado Design Suite Tcl shelll或使用批 Tcl 脚本的信息，请参阅使用 Tcl。

Note: This document is not a complete reference for the available Tcl commands. Instead, see the Vivado Design Suite Tcl Command Reference Guide (UG835) and Vivado Design Suite User Guide: Using Tcl Scripting
(UG894).注意：本文档并非可用 Tcl 命令的完整参考资料。请参阅《Vivado Design Suite Tcl 命令参考指南》(UG835) 和《Vivado Design Suite 用户指南》： 使用 Tcl 脚本(UG894).

Non-Project Mode Tcl Script Example

The following example shows a Tcl script for the BFT sample design included with the Vivado Design Suite. This example shows how to use the design checkpoints for saving the database state at various stages of the flow and how to manually generate various reports. This example script, run_bft_kintex7_project.tcl, is available in the Vivado Design Suite installation at:
下面的示例显示了 Vivado 设计套件中包含的 BFT 示例设计的 Tcl 脚本。该示例演示了如何在流程的各个阶段使用设计检查点保存数据库状态，以及如何手动生成各种报告。此示例脚本 run_bft_kintex7_project.tcl 可在 Vivado Design Suite 安装包中找到，地址为：

<install_dir>/Vivado/2020.2/examples/Vivado_Tutorial
1

You can source the script from the Vivado Tcl shell, or the Tcl Console inside of the Vivado IDE.您可以从 Vivado Tcl shell 或 Vivado IDE 内的 Tcl 控制台获取脚本。

# run_bft_kintex7_batch.tcl
# bft sample design
# A Vivado script that demonstrates a very simple RTL-to-bitstream non-
project batch flow
#
# NOTE: typical usage would be "vivado -mode tcl -source
run_bft_kintex7_batch.tcl"
#
# STEP#0: define output directory area.
#
set outputDir ./Tutorial_Created_Data/bft_output
file mkdir $outputDir
#
# STEP#1: setup design sources and constraints
#
read_vhdl -library bftLib [ glob ./Sources/hdl/bftLib/*.vhdl ]
read_vhdl ./Sources/hdl/bft.vhdl
read_verilog [ glob ./Sources/hdl/*.v ]
read_xdc ./Sources/bft_full_kintex7.xdc
#
# STEP#2: run synthesis, report utilization and timing estimates, write
checkpoint design
#
synth_design -top bft -part xc7k70tfbg484-2
write_checkpoint -force $outputDir/post_synth
report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
report_power -file $outputDir/post_synth_power.rpt
#
# STEP#3: run placement and logic optimzation, report utilization and
timing estimates, write checkpoint design
#
opt_design
place_design
phys_opt_design
write_checkpoint -force $outputDir/post_place
report_timing_summary -file $outputDir/post_place_timing_summary.rpt
#
# STEP#4: run router, report actual utilization and timing, write
checkpoint design, run drc, write verilog and xdc out
#
route_design
write_checkpoint -force $outputDir/post_route
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
report_timing -sort_by group -max_paths 100 -path_type summary -file
$outputDir/post_route_timing.rpt
report_clock_utilization -file $outputDir/clock_util.rpt
report_utilization -file $outputDir/post_route_util.rpt
report_power -file $outputDir/post_route_power.rpt
report_drc -file $outputDir/post_imp_drc.rpt
write_verilog -force $outputDir/bft_impl_netlist.v
write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc
#
# STEP#5: generate a bitstream
#
write_bitstream -force $outputDir/bft.bit
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五、Source Management and Revision Control Recommendations（源文件管理和版本控制推荐）

1、Interfacing with Revision Control Systems

与修订控制系统对接

The methodologies for source management and revision control can vary depending on user and company preference, as well as the software used to manage revision control. This section describes some of the fundamental methodology choices that design teams need to make to manage their active design projects. Specific recommendations on using the AMD Vivado™
Design Suite with revision control systems are provided later in this section. Throughout this section, the term manage refers to the process of checking source versions in and out using a revision control system.
源代码管理和修订控制的方法可以根据用户和公司的偏好以及用于管理修订控制的软件而有所不同。本节介绍了设计团队在管理活动设计项目时需要选择的一些基本方法。本节提供了使用 AMD Vivado™ 设计套件和修订控制系统的具体建议。
设计套件和修订控制系统的具体建议。在本节中，"管理 "一词指的是使用版本控制系统检查源版本的输入和输出过程。

Vivado generates many intermediate files as it compiles a design. This chapter defines the minimum set of files necessary to recreate the design. In some cases, you might want to keep intermediate files to improve compile time or simplify design analysis. Managing additional files is always optional.
Vivado 在编译设计时会生成许多中间文件。本章定义了重新创建设计所需的最小文件集。在某些情况下，您可能希望保留中间文件以缩短编译时间或简化设计分析。管理附加文件始终是可选的。

2、Project vs. Non-Project Build Methodologies

Vivado can compile designs using a project mode or a non-project mode. The Vivado project mode manages file source sets, dependencies, and runs. The project mode can be driven by scripts or interactively in the GUI. Non-project mode customers use scripts to compile their designs directly from the design sources. In this mode, you are responsible for ensuring that your
scripts are up to date and the correct steps are re-run properly as sources are modified. This chapter will primarily focus on how you should revision control Vivado projects, but, non-project customers closely align to the script-based (project) method of revision controlling a Vivado project described in the following sections. Although revision control should not dictate how
your designs are compiled, it is very important to understand the relationship between your chosen compilation method and its impact on your revision control strategy.
Vivado 可使用项目模式或非项目模式编译设计。
Vivado 项目模式管理文件源集、依赖关系和运行。项目模式可由脚本或图形用户界面交互式驱动。
非项目模式客户使用脚本直接从设计源编译设计。在此模式下，您有责任确保您的脚本是最新的，并且在修改源代码时正确地重新运行正确的步骤。
本章将主要介绍如何对 Vivado 项目进行修订控制，但是，非项目客户应密切配合以下各节所述的基于脚本（项目）的 Vivado 项目修订控制方法。虽然修订控制不应决定设计的编译方式，但了解所选编译方法之间的关系及其对修订控制策略的影响非常重要。

3、Project Source Types

RTL, XDC, and DCP

In general, it is recommended that all design sources including RTL, XDC, and DCP files be kept external to the project, and revision controlled independently of the Vivado project. The files should be imported into the project using the add_* tcl commands as opposed to added to the project using the import_*.
一般来说，建议将包括 RTL、XDC 和 DCP 文件在内的所有设计源保存在项目外部，并独立于 Vivado 项目进行修订控制。应使用 add_ tcl 命令将文件导入项目，而不是使用 import_ 命令将文件添加到项目中。**

XCI

The recommended method to revision controlling IP includes:
• Preserving the IP repository
• Checking in the XCI file
修订IP控制的建议方法包括

• 保存 IP 资源库
• 检查 XCI 文件

The IP repository is where the parametrizable IP source code resides and the XCI file contains the parameters to apply to the source code. The combination of these two sources enables Vivado to regenerate the instance of the IP for your specific design. To recreate the project, the generated
IP does not need to be preserved because it can be rebuilt. If you are using custom packaged IP, it is further recommended that you manage the project from which the IP was packaged.
IP 资源库是可参数化的 IP 源代码所在，而 XCI 文件则包含应用于源代码的参数。这两个源的组合使 Vivado 能够为您的特定设计重新生成 IP 实例。要重新创建项目，生成的IP 不需要保留，因为它可以重建。如果您使用的是自定义封装的 IP，还建议您管理封装 IP 的项目。

The lastest version of all AMD IP are installed with Vivado. When upgrading a project to the latest version of Vivado, the AMD IP repository will only contain the latest version of AMD IP. Report IP Status will prompt you to upgrade your design to incorporate the new IP. Depending on the IP changes, design modifications might be necessary to preserve the functionality of your design. It is recommended that you upgrade AMD IP when upgrading to the latest version of Vivado.
所有 AMD IP 的最新版本都与 Vivado 一起安装。将项目升级到最新版本的 Vivado 时，AMD IP 资源库将仅包含最新版本的 AMD IP。报告 IP 状态将提示您升级设计以纳入新的 IP。根据 IP 的变化，可能需要修改设计以保留设计的功能。建议您在升级到最新版本的 Vivado 时升级 AMD IP。

If you do not want to upgrade the IP you must revision control the IP XCI file along with the IP output products that reside in the project.gen directory. The IP cannot be re-customized because the original IP repo no longer exists. The generated output product must be preserved to recreate the design. The output products essentially become project sources. The IP will be locked and cannot be re-customized.
如果不想升级 IP，则必须对 IP XCI 文件和位于 project.gen 目录中的 IP 输出产品进行修订控制。由于原始 IP repo 已不存在，因此无法重新定制 IP。必须保留生成的输出产品才能重新创建设计。输出产品实质上成为项目源。IP 将被锁定，无法重新定制。

Locked IP can also be preserved using an XCIX file (also known as an IP core container). The XCIX file contains the XCI file and the generated output products of the IP. This enables a single file option for revision controlling a generated IP.
锁定的 IP 也可以使用 XCIX 文件（也称为 IP 核容器）来保存。XCIX 文件包含 XCI 文件和 IP 的生成输出产品。这样就可以使用单一文件选项对生成的 IP 进行修订控制。

Note: Locked IP can always be upgraded to use the latest version of the IP and have the restrictions associated with locked IP removed.注：锁定的 IP 可以随时升级到使用最新版本的 IP，并取消与锁定 IP 相关的限制。

The final method for preserving IP uses Tcl. The command write_ip_tcl generates a Tcl script that will recreate the IP based on the current configuration. Replaying the Tcl script will recreate the XCI file. The generated Tcl script does not preserve the IP repository and therefor it is
mandatory that the repository be present when replaying the generated Tcl.
保存 IP 的最后一种方法是使用 Tcl。write_ip_tcl 命令会生成一个 Tcl 脚本，根据当前配置重新创建 IP。重放 Tcl 脚本将重新创建 XCI 文件。生成的 Tcl 脚本不会保留 IP 资源库，因此，在重放生成的 Tcl 脚本时，必须保留存储库。

BD

To revision control a block design, the only file necessary to check in is the BD file itself. Similar to IP, the IP repositories used by the BD must also be present. The BD file contains the configuration of each IP on the canvas and the connections between the IP. The XCI files that reside under the BD source directory contain the IP customizations after parameter propagation
is run during BD validation. Although these files are not required to recreate the design, they will be automatically regenerated when the block diagram is re-validated. When the project is rebuilt from the revision control repository, the BD and the XCI files that reside beneath the BD must be writable. This is a limitation of the current version of Vivado.
要对块设计进行修订控制，唯一需要签入的文件就是 BD 文件本身。与 IP 类似，BD 使用的 IP 资源库也必须存在。BD 文件包含画布上每个 IP 的配置以及 IP 之间的连接。BD 源目录下的 XCI 文件包含在 BD 验证期间运行参数传播后的 IP 自定义。在 BD 验证期间运行后的 IP 自定义。虽然重新创建设计不需要这些文件，但在重新验证框图时，这些文件会自动重新生成。从修订控制库重建项目时，BD 和驻留在 BD 下方的 XCI 文件必须是可写的。这是当前版本 Vivado 的限制。

A second method to preserve a BD is to use the write_bd_tcl command. This command will generate a Tcl script to recreate the BD. The Tcl script preserves the IP customizations, connections between the IP, and all BD properties that effect the design.保存 BD 的第二种方法是使用 write_bd_tcl 命令。该命令将生成一个 Tcl 脚本来重新创建 BD。Tcl 脚本将保留 IP 定制、IP 之间的连接以及影响设计的所有 BD 属性。

Note: To view the differences between two versions of a block diagram, see Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) to learn more about the diffbd utility.注：要查看两个版本框图之间的差异，请参阅《Vivado 设计套件用户指南》： 使用 IP Integrator 设计 IP 子系统 (UG994)，了解有关 diffbd 实用程序的更多信息。

Note: When a block design container is used in a project the source BD resides in the .srcs folder. The instances that are uniquified by parameter propagation reside in the .gen directory. When you restore the project, only the source BD will be visible in the project, and the instance BDs will appear as missing files in the hierarchical sources view. This is expected behavior. Regenerating the parent BD will recreate the block design container instance BDs and recreate the original project.
**注：在项目中使用块设计容器时，源 BD 位于 .srcs 文件夹中。通过参数传播唯一化的实例位于 .gen 目录中。**还原项目时，项目中将只显示源 BD，而实例 BD 将在分层源视图中显示为丢失的文件。这是预期行为。重新生成父 BD 将重新生成块设计容器实例 BD 并重新生成原始项目。

4、Methods to Revision Control a Project

项目修订控制方法

There are two primary methods for revision controlling a project: a script-based method and a source-based method. The script-based method focuses on recreating the project from its sources using a Tcl script. The source-based method revision controls the project sources and the project file (.xpr) directly.项目修订控制有两种主要方法：基于脚本的方法和基于源代码的方法。基于脚本的方法主要是使用 Tcl 脚本从项目源重新创建项目。基于源代码的方法则直接对项目源代码和项目文件（.xpr）进行修订控制。

Note: An alternative to the two methods is to revision control the entire Vivado project directory. The drawback to this method is the large amount of disk space required. 注：除上述两种方法外，还有一种方法是对整个 Vivado 项目目录进行修订控制。这种方法的缺点是需要大量磁盘空间。

Script-based Revision Control Methodology基于脚本的修订控制方法

The following steps outline how revision controlling a project using a script-based method can be achieved.以下步骤概述了如何使用基于脚本的方法对项目进行修订控制。

1. Keep source files external to the project. Ideally, the source files are kept outside of the Vivado build directory.

2. Revision control the source repository. All sources should be managed by the revision control system.
   IMPORTANT! When Vivado is using the source files, they should be writable.

3. Generate a script to recreate the design.

4. Revision control the script. Once the script is created, it is important to manage this file as a source too. As the design changes, this script must be updated to accommodate new sources or to capture new design configurations. It is important that this script is managed like any other design source.

5. Test your methodology. Ideally, to ensure no files are missed and the design rebuilds completely from design sources using a script, the design would be regressed at a regular cadence. By rebuilding the design regularly, any issues with the revision control methodology can be caught and addressed in a timely manner.

6. 将源文件保存在项目外部。理想情况下，源文件保存在 Vivado 构建目录之外。

7. 对源代码库进行修订控制。所有源代码都应由修订控制系统管理。
   重要！当 Vivado 使用源文件时，它们应是可写的。

8. 生成脚本以重新创建设计。

9. 对脚本进行版本控制。创建脚本后，也要将此文件作为源文件进行管理。当设计发生变化时，必须更新脚本以适应新的源文件或捕捉新的设计配置。重要的是，要像管理其他设计源一样管理该脚本。

10. 测试方法。理想情况下，为确保不遗漏任何文件，并使用脚本从设计源完整地重建设计，应定期对设计进行回归。通过定期重建设计，可以及时发现并解决修订控制方法中的任何问题。

Generating a Script to Recreate a Design生成脚本以重现设计

For a project flow, a script to recreate your design can be generated manually or by using the write_project_tcl command. The advantages of manually creating the script, is that it remains short and well organized. The drawback is that you could easily miss a project setting and fail to faithfully recreate the original design. 对于项目流程，可以手动或使用 write_project_tcl 命令生成脚本来重新创建设计。手动创建脚本的优点是篇幅短小，条理清晰。缺点是很容易遗漏项目设置，无法忠实重现原始设计。

Any settings modified when the design is open using either the GUI or the Tcl console must be reflected back to the script or there is a risk the design is identical to the original project. Alternatively, the write_project_tcl script is robust in ensuring all files are captured appropriately. Its versatility results in a more complicated and more verbose script. Regardless of how this script is generated, it must be maintained as the design evolves
设计打开时修改的任何设置必须反映到脚本中，否则设计有可能与原始项目相同。另外，write_project_tcl 脚本在确保适当捕获所有文件方面非常强大。它的多功能性导致脚本更加复杂和冗长。无论该脚本是如何生成的，都必须随着设计的发展而加以维护

Note: write_project_tcl recreates the design as originally created by the user. For designs using IP integrator, propagated parameters do not reflect in the recreated design until validate_bd_design is re-run.
注意：write_project_tcl 将重新创建用户最初创建的设计。对于使用 IP 集成器的设计，在重新运行 validate_bd_design 之前，传播的参数不会反映在重新创建的设计中。

Write_project_tcl provides two options to preserve block diagrams contained in the project. The default option is to recreate the BD from Tcl. In this case, write_project_tcl calls write_bd_tcl for each BD in the project. The resulting write_project_tcl script contains the Tcl commands necessary to recreate each BD in the project. Alternatively, the BDs can be included directly as a project source. In this case, the resulting Tcl script adds each BD file,
from the original project, directly to the project it recreates. If manually creating this project script, a similar approach can be taken.

Write_project_tcl 提供了两个选项来保留项目中包含的框图。默认选项是从 Tcl 重新创建 BD。在这种情况下，write_project_tcl 会为项目中的每个 BD 调用 write_bd_tcl。生成的 write_project_tcl 脚本包含重新创建项目中每个 BD 所需的 Tcl 命令。或者，也可以直接将 BD 作为项目源代码。在这种情况下，生成的 Tcl 脚本会添加每个 BD 文件、直接添加到它重新创建的项目中。如果手动创建此项目脚本，也可以采用类似的方法。

Source-based Revision Control Methodology基于源的修订控制方法

The source-based method for preserving a Vivado project relies on the separation of project sources from their generated output products. Because 2020.2, all files added to a project reside In the project.srcs directory. All tool-generated output products reside in a parallel directory called project.gen. The source-based method of revision controlling can be achieved by:
基于源代码的 Vivado 项目保存方法依赖于项目源代码与其生成的输出产品的分离。自 2020.2 版起，添加到项目中的所有文件都位于 project.srcs 目录中。所有工具生成的输出产品都位于名为 project.gen 的并行目录中。基于源代码的修订控制方法可以通过以下方式实现：

• Keeping source files external to the project. Ideally, the source files are kept outside of the Vivado build directory.
• Managing revision control of the source repository. All sources should be managed by the revision control system.

• 将源文件保存在项目外部。理想情况下，源文件保存在 Vivado 构建目录之外。
• 管理源代码库的修订控制。所有源代码都应由修订控制系统管理。

IMPORTANT! When Vivado is using the source files, they should be writable.
重要！当 Vivado 使用源文件时，它们应是可写的。

• Managing revision control of the project.xpr file.
• Managing revision control of the project.srcs directory.
• Testing your methodology. Ideally, to ensure no files are missed and the design rebuilds completely from design sources using a script, the design would be regressed at a regular cadence. By rebuilding the design regularly, any issues with the revision control methodology can be caught and addressed in a timely manner.

• 管理 project.xpr 文件的修订控制。
• 管理 project.srcs 目录的修订控制。
  - 测试方法。理想情况下，为确保不遗漏任何文件，并使用脚本从设计源完全重建设计，应定期对设计进行回归。通过定期重建设计，可以及时发现并解决修订控制方法中的任何问题。

The project can be re-created by restoring the project.srcs directory and the project.xpr file. The project.xpr file can be opened and the user can proceed with synthesis and implementation.
可以通过恢复 project.srcs 目录和 project.xpr 文件来重新创建项目。打开 project.xpr 文件后，用户即可继续进行综合和执行。

Comparison between Script-based and Source-based Revision Control Methodologies
基于脚本和基于源代码的修订控制方法比较

下表比较了 Vivado 项目的两种修订控制方法。

The following table compares the two methods of revision controlling a Vivado project.


Comparing the files that need to be revision controlled, the script based is much smaller. No matter if you auto generate the build script or manually create it, the only thing that needs to be revision controlled is the script. Using the source based method, the XPR file and the .srcs directory both need to be managed. These are much bigger than a text script. The benefits to using the source-based methodology is that the project is available immediately. Once you check out the XPR file and the .srcs directory, you can open the project. Using the script-based methodology, the script needs to run to completion before you can open the project. In both cases, AMD does not tend to revision control output products, and therefore to recompile the designs, there will be considerable compute time spent recreating the output products. In both cases, if an external cache is maintained, the compile time can be reduced significantly.
比较需要进行修订控制的文件，基于脚本的文件要小得多。不管是自动生成构建脚本还是手动创建，需要进行修订控制的只有脚本。使用基于源代码的方法，XPR 文件和 .srcs 目录都需要管理。这些文件要比文本脚本大得多。使用基于源代码的方法的好处是，项目可以立即使用。一旦签出 XPR 文件和 .srcs 目录，就可以打开项目。而使用基于脚本的方法，脚本需要运行完成后才能打开项目。在这两种情况下，AMD 都不倾向于对输出产品进行修订控制，因此要重新编译设计，需要花费大量的计算时间来重新创建输出产品。在这两种情况下，如果保持外部缓存，编译时间都可以大大缩短。

The remaining items are similar between the two flows. In both cases, all external sources need to be revision controlled separately from the project. Also, in both cases, AMD does not fully support having BDs or IPs completely read-only. BDs must be writable to run validation. Running
validation updates XCI files under the BD directory structure even if there are no design changes. IP can be read-only, but if they are in this state the IP will be locked and unable to upgrade.
两种流程的其余项目类似。在这两种情况下，所有外部源都需要与项目分开进行修订控制。此外，在这两种情况下，AMD 都不完全支持 BD 或 IP 完全只读。BD 必须可写才能运行验证。运行验证会更新 BD 目录结构下的 XCI 文件，即使没有设计变更。IP 可以只读，但如果处于这种状态，IP 将被锁定，无法升级。

5、Other Files to Revision Control

The project manages many other types of files required to rebuild a design. Following are a few examples:
• Simulation test benches
• HLS IP
• Pre/post Tcl hook scripts used for synthesis or implementation
• Incremental compile DCPs
• ELF and MEMDATA files
• AI Engine archives
该项目管理重建设计所需的许多其他类型的文件。以下是几个例子：

• 仿真测试台
• HLS IP
• 用于综合或实现的前/后 Tcl 钩子脚本
• 增量编译 DCP
• ELF 和 MEMDATA 文件
• AI 引擎存档

Pay special attention to files that are used in the project but are not added directly. For example, files that are referenced by a set_property command that is not added to the project sources.These files should reside external to the project directory structure and revision controlled separately.
特别注意项目中使用但未直接添加的文件。例如，未添加到项目源中的 set_property 命令引用的文件。这些文件应位于项目目录结构之外，并单独进行修订控制。

6、Output Files to Optionally Revision Control

输出文件到可选版本控制

Following is a list of additional files you might consider revision controlling:
• Simulation scripts for third-party simulators generated by export_simulation. Because these are typically hand-off files between design and verification, you might want to snapshot them at different stages of the design process.
• XSA files. These are hardware hand-off files between Vivado and AMD Vitis™ software platform.
• Bitsteams/PDIs.
• LTX files for hardware debug.
• Intermediate DCP files created during the flow.
• IP output products.
以下是您可以考虑进行修订控制的其他文件列表：

• export_simulation 生成的第三方仿真器仿真脚本。
  由于这些文件通常是设计与验证之间的交接文件，因此可能需要在设计流程的不同阶段对其进行快照。
• XSA 文件。
  这些是 Vivado 和 AMD Vitis™ 软件平台之间的硬件交接文件。
• Bitsteams/PDIs 文件。
• 用于硬件调试的 LTX 文件。
  - 流程中创建的中间 DCP 文件。
• IP 输出产品。

Archiving Designs归档设计

The archive_design command can compress your entire project into a zip file. This command has several options for storing sources and to run results. Essentially, the entire project is copied locally in the memory and then zipped into a file on the disk while leaving the original project intact. This command also copies any remote source into the archive.

archive_design 命令可将整个项目压缩为一个 zip 文件。该命令有多个选项，可用于存储源代码和运行结果。基本上，整个项目会复制到本地内存中，然后压缩到磁盘上的一个文件中，同时保留原始项目。该命令还可将任何远程源代码复制到归档文件中。

This feature is useful for sending your design description to another person or to store as a self contained entity. You might also need to send your version of vivado_init.tcl if you are using this file to set specific parameters or variables that affect the design. For more information, see the following resources:
• Vivado Design Suite User Guide: System-Level Design Entry (UG895)
• Vivado Design Suite QuickTake Video: Creating Different Types of Projects
• Vivado Design Suite QuickTake Video: Managing Sources with Projects

这一功能对于将设计说明发送给他人或作为自包含实体存储非常有用。如果使用 vivado_init.tcl 文件设置影响设计的特定参数或变量，还可能需要发送 vivado_init.tcl 版本。有关详细信息，请参阅以下资源：

• Vivado Design Suite 用户指南： 系统级设计输入 (UG895)
• Vivado Design Suite QuickTake 视频： 创建不同类型的项目
• Vivado Design Suite QuickTake 视频： 使用项目管理源代码

六、Additional Resources and Legal

1、Finding Additional Documentation查找其他文件

Documentation Portal文档门户网站

The AMD Adaptive Computing Documentation Portal is an online tool that provides robust search and navigation for documentation using your web browser. To access the Documentation Portal, go to https://docs.xilinx.com.
AMD 自适应计算文档门户是一种在线工具，可使用网络浏览器提供强大的文档搜索和导航功能。要访问文档门户，请访问 https://docs.xilinx.com。

Documentation Navigator文档导航器

Documentation Navigator (DocNav) is an installed tool that provides access to AMD Adaptive Computing documents, videos, and support resources, which you can filter and search to find information. To open DocNav:
文档导航器 (DocNav) 是一种已安装的工具，用于访问 AMD Adaptive Computing 文档、视频和支持资源，您可以通过过滤和搜索来查找信息。要打开 DocNav，请:

• From the AMD Vivado™ IDE, select Help → Documentation and Tutorials.
• On Windows, click the Start button and select Xilinx Design Tools → DocNav.
• At the Linux command prompt, enter docnav.

• 在 AMD Vivado™ 集成开发环境中，选择帮助 → 文档和教程。
• 在 Windows 中，单击 "开始 "按钮并选择 Xilinx Design Tools → DocNav。
• 在 Linux 命令提示符下，输入 docnav。

Design Hubs设计中心

AMD Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs:
• In DocNav, click the Design Hubs View tab.
• Go to the Design Hubs webpage.

Note: For more information on DocNav, see the Documentation Navigator webpage.

AMD 设计中心提供按设计任务和其他主题组织的文档链接，您可以利用这些链接学习关键概念并解决常见问题。要访问设计中心，请

• 在 DocNav 中，单击 Design Hubs View 选项卡。
• 转到设计集线器网页。

注：有关 DocNav 的更多信息，请参阅文档导航网页。

2、Support Resources

For support resources such as Answers, Documentation, Downloads, and Forums, see Support.
有关解答、文档、下载和论坛等支持资源，请参阅支持。

3、References

These documents provide supplemental material useful with this guide:

1. Vitis Model Composer User Guide (UG1483)
2. Vivado Design Suite User Guide: High-Level Synthesis (UG902)
3. UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)
4. Reference System: Kintex-7 MicroBlaze System Simulation Using IP Integrator (XAPP1180)
5. Vivado Design Suite Tcl Command Reference Guide (UG835)
6. Vivado Design Suite Tutorial: High-Level Synthesis (UG871)
7. Vivado Design Suite Tutorial: Design Flows Overview (UG888)
8. Vivado Design Suite User Guide: Using the Vivado IDE (UG893)
9. Vivado Design Suite User Guide: Using Tcl Scripting (UG894)
10. Vivado Design Suite User Guide: System-Level Design Entry (UG895)
11. Vivado Design Suite User Guide: Designing with IP (UG896)
12. Vitis Model Composer User Guide (UG1483)
13. MicroBlaze Processor Embedded Design User Guide (UG1579)
14. Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
15. Vivado Design Suite User Guide: Logic Simulation (UG900)
16. Vivado Design Suite User Guide: Synthesis (UG901)
17. Vivado Design Suite User Guide: Using Constraints (UG903)
18. Vivado Design Suite User Guide: Implementation (UG904)
19. Vivado Design Suite User Guide: Hierarchical Design (UG905)
20. Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)
21. Vivado Design Suite User Guide: Programming and Debugging (UG908)
22. Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)
23. Vivado Design Suite User Guide: Getting Started (UG910)
24. ISE to Vivado Design Suite Migration Guide (UG911)
25. Vivado Design Suite Tutorial: Embedded Processor Hardware Design (UG940)
26. Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)
27. UltraFast Design Methodology Guide for FPGAs and SOCs (UG949)
28. Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
29. Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)
30. UltraFast Embedded Design Methodology Guide (UG1046)
31. Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)
32. Vivado Design Suite Tutorial: Creating, Packaging Custom IP (UG1119)
33. Vivado Design Suite Documentation

4、Training Resources

AMD provides a variety of training courses and QuickTake videos to help you learn more about the concepts presented in this document. Use these links to explore related training resources:
AMD 提供各种培训课程和 QuickTake 视频，帮助您进一步了解本文档中介绍的概念。请使用这些链接查看相关培训资源：

1. Designing FPGAs Using the Vivado Design Suite 1 Training Course
2. Designing FPGAs Using the Vivado Design Suite 2 Training Course
3. Vivado Design Suite QuickTake Video: Vivado Design Flows Overview
4. Vivado Design Suite QuickTake Video: Getting Started with the Vivado IDE
5. Vivado Design Suite QuickTake Video: Targeting Zynq Devices Using Vivado IP Integrator
6. Vivado Design Suite QuickTake Video: Partial Reconfiguration in Vivado Design Suite
7. Vivado Design Suite QuickTake Video: Simulating with Cadence IES in Vivado
8. Vivado Design Suite QuickTake Video: Simulating with Synopsys VCS in Vivado
9. Vivado Design Suite QuickTake Video: I/O Planning Overview
10. Vivado Design Suite QuickTake Video: Using Vivado Design Suite with Revision Control
11. Vivado Design Suite QuickTake Video: Creating Different Types of Projects
12. Vivado Design Suite QuickTake Video: Managing Sources with Projects
13. Vivado Design Suite QuickTake Video: Managing Vivado IP Version Upgrades
14. Vivado Design Suite QuickTake Video Tutorials

5、Revision History

6、Please Read: Important Legal Notices