TM4C123-JTAG_xds100v2烧录器引脚定义

本文摘录于TI官方手册SPMA075，主要内容是对JTAG的认识及硬件设计。

一、JTAG的基本认识

JTAG接口主要是四个引脚
TMS 、TDI 、TDO、TCK

At power on, the TAP state machine (see Figure 1) is initialized to be in Test Logic Reset state. It moves from one state to another based on the TMS value (shown as logic 0 or 1 on the transition arrow) with every TCK. Once the state machine enters the Shift state, the TDI pin is used to serially shift in the IR or DR. At the same time, the value captured in the shift register during the Capture state is shifted out on to the TDO. When the Update state is executed, the value shifted in during the Shift state is updated to the TAP for the next JTAG cycle.

JTAG核心是TAP状态机。上电后初始化为Test Logic Reset state，它根据每一个TCK时钟边沿TMS的逻辑电平进行状态转移。当进入移位状态时，TDI的数据移入IR或DR寄存器，当进入捕获状态时，移位寄存器中的Capture state 移出至TDO.当执行更新状态时，在移位状态移入移位寄存器中的数据被更新以准备下一个循环周期。

JTAG 可以有两种连接方式
点对点

菊花链

菊花链模式下速度较慢，因为需要额外的移位操作以使每个TAP到正确的状态。
JTAG access is slower as additional shifts are required to bring each device TAP to the correct state

JTAG还可以有额外的两个引脚
Besides the four JTAG pins, there are two more pins available on some devices: TRST and RTCK.
• TRST: Test Reset. This pin is an optional pin and can be used to reset the JTAG TAP state machine. It is an active low signal.
• RTCK: Return TCK. This is a clock that is sourced by the device. When available, the TDO is sampled with this clock allowing for higher JTAG operation frequency. This is also referred to as adaptive clocking.

二、JTAG的引脚定义

1.四种标准的JTAG接口

2.TM4C12X系列单片机JTAG硬件设计

适用于TM4C12X系列的仿真器
XDS100V2、XDS100V3、XDS200、XDS560V2

Stellaris ICDI、I-jet、ULINK2

三、TM4C12X JTAG接口行为

JTAG的功能受BOOTCFG寄存器中位0和位1的影响

All TM4C12x devices have the BOOTCFG register. This register influences the behavior of the device boot after a power on reset. One of the functions is the ability to disable the JTAG function without
configuring the GPIO port C as GPIO’s. This is achieved by clearing the bits 0 and 1. For more information, see device-specific data sheet. When the bits are cleared, the JTAG function is disabled.

当出现引脚配置错误时，可执行Unlock Sequence。

当初次使用时，可通过TEST CONNECTION功能验证连接的正确性。

If the JTAG IR and DR Integrity scan-test succeeds, it means that the device core is out of reset and may
not have initialized itself. If, however, the integrity scan-test fails, the issue is in the power up process.
The following steps must be followed to make sure every known cause is eliminated till the source of the
issue is found:

1. Check with a digital multi-meter that the VDD and VDDA supply rails are 3.3 V.
   (a) If not, then check the power supply aspect of the design.
2. Check with a digital multi-meter that the VDDC rail is 1.2 V.
   (a) If not and providing a power from an external power source, make sure that the current limit is set
   around 150 mA.
3. If the VDDC rail is at 1.2 V, make sure that the capacitance on the rail is as per the device-specific
   data sheet and the layout of the capacitors are as per the system design guidelines and application
   reports (see Section 8).
4. Check whether the JTAG header is correctly mounted and the TDIS pin (if available) is connected to
   GND.
5. Check on the JTAG header the VTREF pin is 3.3 V.
6. Check whether the Reset Pin of the microcontroller is at 3.3 V.
   (a) If not, connect an external pull up.
7. If using an external crystal oscillator, connect an oscilloscope on pin OSC0.
   (a) If the crystal is not oscillating, check the solder on the crystal and capacitors.
   (b) Always use the recommended crystals as per the device-specific data sheet.
8. If not using an external crystal oscillator, make sure that the pin OSC0 is connected to GND.
9. If using a TM4C129x device with integrated PHY, make sure that the RBIAS resistor is populated as
   per device-specific data sheet recommendation.