HDLBits verlog刷题-Finding bugs in code-02_NAND_this three-input nand gate doesn't work. fix the b

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HDLBITs_reading simulations

题目描述-Bugs nand3

This three-input NAND gate doesn’t work. Fix the bug(s).

You must use the provided 5-input AND gate:
module andgate ( output out, input a, input b, input c, input d, input e );
简言之
用一个5输入的与门模块-------实现3输入与非

参考资料

Verilog中提供的逻辑门和开关模型的定义及用法总结

代码部分

//要一个3输入的与非门
//用一个5输入的与门实现---3输入与非
module top_module (input a, input b, input c, output out);//
    
    //原来错误语句,
    //andgate inst1 ( a, b, c, out );

    /**正确语句***/
    //定义与门输出
    wire and_out;
    //写5输入与门--**注意输出放到最前
    andgate inst1 ( and_out, a, b, c, 1'b1,1'b1);
    //与非门输出
    assign out=~and_out;
endmodule
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