Aurora_aurora协议详解

一、基于 Aurora 8/10b 光纤传输协议

1、SFP+光电转换模块

2、Aurora协议简介

                                                        图 1 Aurora 64B/66B 通道概述

二、系统实现

2.1、Aurora 64/66b IP 核配置

图2 Aurora 64B/66B IP核心配置

在s_axi_tx_tvalid和s_axi_tx_tready同时为高时，发送数据。

在m_axi_tx_tvalid为高时，接收数据。

代码如下，m_axis_tvalid && m_axis_tready为1时，数据累加

`timescale 1ns / 1ps
 
 
module user_req_generate #(
	parameter USER_WR_DATA_WIDTH    = 64	
)(
	input          						   clk,
	input          						   reset,
 
	input                   			   lane_up,
	input                   			   channel_up,
 
	output reg              			   m_axis_tvalid,
	input                   			   m_axis_tready,
	output reg [USER_WR_DATA_WIDTH-1:0]    m_axis_tdata,
	output     [USER_WR_DATA_WIDTH/8-1 :0] m_axis_tkeep,
	output reg                             m_axis_tlast                      
 
);
	
	localparam CNT_MAX = 150;
 
	reg [7:0]  reset_timer;
	reg        reset_sync_d0;
	reg        reset_sync_d1;
	reg        reset_sync;
	wire 	   vio_wr;
	reg        vio_wr_d0;
	reg        vio_wr_d1;
	reg        vio_wr_d2;
	reg [7:0]  cnt;
 
	assign m_axis_tkeep = {USER_WR_DATA_WIDTH/8{1'b1}};
	
	always @(posedge clk or posedge reset) begin
		if (reset) 
			reset_timer <= 8'd0;
		else if (~ (lane_up | channel_up) ) 
			reset_timer <= 8'd0;
		else if (reset_timer <= 8'haf)
			reset_timer <= reset_timer + 1'b1;
		else 
			reset_timer <= reset_timer;
	end
 
	always @(posedge clk or posedge reset) begin
		if (reset)begin
			reset_sync_d0 <= 1'b1;
			reset_sync_d1 <= 1'b1;
			reset_sync    <= 1'b1;
		end		
		else begin
			reset_sync_d0 <= reset_timer <= 8'haf;
			reset_sync_d1 <= reset_sync_d0;
			reset_sync    <= reset_sync_d1;
		end		
	end
 
 
	always @(posedge clk) begin
		vio_wr_d0 <= vio_wr;
		vio_wr_d1 <= vio_wr_d0;
		vio_wr_d2 <= vio_wr_d1;
	end
 
 
	always @(posedge clk) begin
		if (reset_sync) 
			cnt <= 8'd0;
		else if (cnt == CNT_MAX && m_axis_tvalid && m_axis_tready) 
			cnt <= 8'd0;
		else if (m_axis_tvalid && m_axis_tready)
			cnt <= cnt + 1;
	end
 
	always @(posedge clk) begin
		if (reset_sync) 
			m_axis_tvalid <= 1'b0;
		else if (vio_wr_d1 && ~vio_wr_d2) 
			m_axis_tvalid <= 1'b1;
		else if (cnt == CNT_MAX && m_axis_tvalid && m_axis_tready)
			m_axis_tvalid <= 1'b0;
	end
 
	always @(posedge clk) begin
		if (reset_sync) 
			m_axis_tlast <= 1'b0;
		else if (cnt == CNT_MAX - 1 && m_axis_tvalid && m_axis_tready) 
			m_axis_tlast <= 1'b1;
		else if (cnt == CNT_MAX && m_axis_tvalid && m_axis_tready)
			m_axis_tlast <= 1'b0;
	end
 
	always @(posedge clk) begin
		if (reset_sync) 
			m_axis_tdata <= 0;
		else if (m_axis_tvalid && m_axis_tready) 
			m_axis_tdata <= m_axis_tdata + 1;
		else 
		    m_axis_tdata <= m_axis_tdata;
	end
vio_0 vio_0 (
  .clk(clk),                // input wire clk
  .probe_out0(vio_wr)  // output wire [0 : 0] probe_out0
);
endmodule

 三、上板验证

讲ZCU102板作为发射端，VC707板作为接收端，光口10G模块测试收发。

ZCU102发送从0开始的递增数

VC707接受到0开始的递增数，验证成功。

四、后续工作

        后续将用PCIE与Aurora进行数据交互

        需要改进的地方：

对于TX端，可连接一个异步FIFO，这样解决了数据源的数据到aurora IP核tx_data的跨时钟域问题。tx_fifo的输入和rx_fifo的输出，tx_fifo的写时钟和rx_fifo的读时钟速率小于user_clk（156.25Mhz）,所以对于可以向tx_fifo一直写入数据，rx_fifo中也一直由数据读出.

与aurora 64B66B 发送端 AXI4-Stream接口 相连的FIFO设置_aurora fifo-CSDN博客

Aurora使用技巧详解_aurora的gtselections-CSDN博客

FIFO用法详解（附有代码）_fifo读使能代码-CSDN博客