DP1.4协议 关键特性总结_dp1.4速率

写在前面：本片文章基于DP1.4标准的draft版本，但是和最终版本已经没有太大差别。

总结了Main-Link, AUX, HPD, SST, MST, Training Syntax and Sequence等重要特性。

DP传输信号的关键部分

从Source到Device的传输，主要由主链路，AUX通道和HPD构成。

DP Main-Link 主链路

单向，1条或2条或4条 AC耦合的、双端差分高速信号链路

链路传输速率(Link rate):  1.62Gbps, 2.7Gbps, 5.4Gbps, 8.1Gbps/lane. 如果是多条链路同时传输，那么所有通道必须工作在同一个link rate。带宽如下：

没有单独的时钟链路。

编码方式：8b/10b编码。易于纠错且利于DC均衡。

Pixel Data Mapping的例子: 

AUX 通道

AC耦合，双端（50欧姆端接电阻），差分信号

双向，半双工，通过AUX通道的通讯可以实现链路管理和设备控制

主(Master)：DP Source

从(Slave)：DP Sink

传输方式：1Mbps曼彻斯特编码。如果支持Fast AUX transaction, 那么可以到720Mbps

基本原则（语法）：AUX transaction总是由Upstream发起。 Source和Sink可以通过Native AUX或者I2C over AUX或者USB over AUX的方式通讯。如果通过USB over AUX通讯，那么需要支持Fast AUX。

硬件设计规则：

The upstream DP device must weakly pull down the AUX+ line to GND and weakly pull up the AUX- line to DP_PWR each with a resistor in the range 10kΩ to 105kΩ between the AC-coupling capacitor and the upstream device connector to assist detection of the upstream DP device and powered upstream DP device by the downstream device. A nominal 100kΩ resistor value
is recommended.（Source和Sink两端对AUX有上拉和下拉，应用中汽主要目的是维持驱动能力）
All downstream devices must have AC-coupling capacitors, regardless of whether they implement upstream DP device detection. The downstream devices must very weakly pull up AUX+ line and very weakly pull down AUX- line with 1MΩ (±5%) resistors between the downstream device connector and the AC-coupling capacitors. When AUX+ line DC voltage is L level, it means an upstream DP device is connected. When AUX- line DC voltage is H level, it means that a powered upstream DP device is connected.（耦合电容对AUX通道也非常重要，一般是0.1uF）
 

HPD

HPD是由DP Sink发起的单向中断信号

有三种HPD scenario：

Case1: DP sink接入，Sink端拉低HPD电平发起HPD中断。HPD脉冲宽度在0.25ms~2ms之间。DPTX需要再IRQ_HPD_Pulse上升沿后的100ms以内读DPRX DPCD的设备状态。2ms是HPD脉冲的超时时间。

Case2: DP sink断开连接。当HPD脉冲的低电平持续时间超过2ms，DPTX会等待HPD电平被重新拉高。

Case3: Hot Plug/Re-plug. DPTX也要读DPCD。

HPD信号检测标准:

HPD de-bounce time:

- DPTX are recommended to implement de-bouncing of the HPD signal on an external connection
- A period of 100 ms is recommended for the detection of an HPD connect event.
比如 the event, “HPD High”, is confirmed only after HPD has been asserted continuously for 100 ms.

SST模式

Main-Link: 传输

Link and device management over AUX：发现，配置和维护Link连接。AUX访问DPCD就是这个目的。

Link Layer: Provides services as instructed or requested by the Stream/Link Policy makers

Source 和 Sink devices都必须有下面两个policy makers：

Stream Policy Maker: manages the transport of the stream

Link Policy Maker: manages the link and is responsible for keeping the link synchronized.

Lanes data rate确立：DPRX必须通过DPCD寄存器描述其接收能力。DPTX在读取DPRX DPCD后，必须配置DPCD Link Filed
Configuration reg. 然后开始link training。Mainlink通道的信号传输稳定性和 PCB设计, DP 线, DP connector都有关系。

SST同步传输服务：

数据mapping：Packing/Unpacking，Stuffing/Unstuffing，Framing/Unframing，Inter-lane skewing/de-skewing

Stream CLK regeneration

Main stream attribute data insertion

Secondary-Data Packet(SDP) optional insertion

AUX通道

AUX通道的协议沟通最初是由DP Source发起的

Diagram of DPTX: 超时时间400us

Diagram of DPRX: 超时时间300us

判决：

AUX 通道服务

数据流传输初始化顺序

1） Stream Policy maker在初始化传输之前需要先做下面的事情：

读Sink的EDID；设置Main stream属性数据和CEA861 INFOFRAME

从Link Policy Maker获取数据：RX接收能力（Number and types of ports available in RX）；Link configuration(Total link bandwidth); Link status(Synchronized? Excessive error symbols?)

2) When a stream is ready for transport, the Stream Policy Maker must start the transport of isochronous stream along with
stream attributes data.

Link Training:

DPTX检测到正确的HPD事件后，Link Policy Maker初始化Link Training

包括三种Training情况：Full Link training; Fast Link training; No link training

Link training的关键指标： CR和EQ

Clock Recovery (CR)： Link training begins with the Clock Recovery (CR) sequence. 时钟锁定和差分电压Vpp设置. Locks the receiver CR (clock recovery) PLL when successful.

Channel Equalization (EQ)：Symbol-Lock & Inter-lane Alignment and Pre-emphasis setting. 

注意： Training发生在读RX DPCD，EDID之后。

Link training for DPCD：

CR time out: 100us

EQ time out: Optional. 400us, 4ms, 8ms, 12ms,16ms

在Fast training中，没有AUX transaction

CR：

所有Devices必须支持TPS1和TPS2。 支持HBR2的Device还必须支持TPS3。支持HBR3的Device必须支持TPS4

CR建立过程：

The receiver may defer setting LANEx_CR_DINE bits until the optimization is completed

If the receiver keeps the same value in ADJUST_REQUEST_LANEx_x, increase the voltage swing and/or pre-emphasis level according to the request

Unless all the LANEx_CR_DONE bit are set, the transmitter must read the ADJUST_REQUEST_LANEx_x, increease the and/or pre-emphasis level according to the request voltage swing

EQ建立过程：

The Receiver(Downstream) must use the recognition of this training pattern to decide whether the channel equalization is successful or not.

允许的Vdiff_pp和PEQ 组合

Training何时结束？

SDP

Pin assignment:

Connection

附录

DPCD地址