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FPGA输出lvds信号点亮液晶屏_fpga rgb转lvds

fpga rgb转lvds

概述

        该方案用于生成RGB信号,通过lvds接口驱动逻辑输出,点亮并驱动BP101WX-206液晶屏幕。

参考:下面为参考文章,内容非常详细。Xilinx LVDS Output——原语调用_vivado原语_ShareWow丶的博客icon-default.png?t=N7T8http://t.csdn.cn/Zy37p

功能描述

顶层逻辑结构简略图

        MMCM模块为时钟模块,负责将系统时钟变频与输出,产生各模块所需要的时钟;data_generator模块用于生成各种数据与信号,并传输给lvds_output_driver模块,lvds_output_driver模块将这些数据进行并串转换并按指定的lvds格式输出给液晶屏。

3 模块详细设计

        MMCM模块用于时钟的变频与输出,data_generator模块用于生成8bit RGB数据,行场同步信号(h_sync、v_sync)和数据使能信号data_en,并传输给lvds_output_driver模块,该模块将这些数据进行并串转换并按指定格式输出给液晶屏。具体详细设计图如下:

逻辑顶层详细结构图

        3.1 MMCM模块

        以下为时钟模块MMCM的接口示意图输出65Mhz和455Mhz的时钟,输出locked作为其他模块的复位信号,改模块采用IP核实现。

MMCM模块接口示意图

        3.2 Data_generator模块设计

        手册中给出的时序信息如下图:

手册时序信息

        依照这样的逻辑,画出大致的设计时序图:

时序图01

时序图02

        3.3 lvds_output_driver模块设计

        该模块的详细设计如下:

lvds_output_driver模块逻辑结构图

        手册中的输出逻辑时序如下:

4 详细代码设计

        4.1 data_generator模块详细设计

  1. /*
  2. this module is used for data generation
  3. BP101WX1-206
  4. 1280 * 800 pixel
  5. */
  6. //count H_SYNC
  7. always @(posedge i_clk_65mhz or posedge i_rst) begin
  8. if (i_rst) begin
  9. cnt_h <= 0;
  10. end
  11. else if (end_cnt_h) begin
  12. cnt_h <= 0;
  13. end
  14. else begin
  15. cnt_h <= cnt_h + 1;
  16. end
  17. end
  18. assign end_cnt_h = cnt_h == (H_TOTAL - 1);
  19. //count V_SYNC
  20. always @(posedge i_clk_65mhz or posedge i_rst) begin
  21. if (i_rst) begin
  22. cnt_v <= 0;
  23. end
  24. else if (end_cnt_h) begin
  25. if (end_cnt_v) begin
  26. cnt_v <= 0;
  27. end
  28. else begin
  29. cnt_v <= cnt_v + 1;
  30. end
  31. end
  32. end
  33. assign end_cnt_v = end_cnt_h && (cnt_v == (V_TOTAL - 1));
  34. //OUTPUT h_sync v_sync DE
  35. always @(posedge i_clk_65mhz or posedge i_rst) begin
  36. if (i_rst) begin
  37. o_h_sync <= 1;
  38. end
  39. else if ((cnt_h == H_FRONT - 1) || (cnt_h == H_FRONT + H_SYNC - 1)) begin
  40. o_h_sync <= ~o_h_sync;
  41. end
  42. end
  43. always @(posedge i_clk_65mhz or posedge i_rst) begin
  44. if (i_rst) begin
  45. o_v_sync <= 1;
  46. end
  47. else if ((cnt_v == V_FRONT - 1 && end_cnt_h) || (cnt_v == V_FRONT + V_SYNC - 1 && end_cnt_h)) begin
  48. o_v_sync <= ~o_v_sync;
  49. end
  50. end
  51. always @(posedge i_clk_65mhz or posedge i_rst) begin
  52. if (i_rst) begin
  53. o_data_en <= 0;
  54. end
  55. else if ((cnt_h == H_BLANK - 1 && cnt_v >= V_BLANK) || (cnt_h == H_TOTAL - 1 && cnt_v >= V_BLANK)) begin
  56. o_data_en <= ~o_data_en;
  57. end
  58. end
  59. //RGB data generation
  60. assign x_cnt = (cnt_h >= H_BLANK)? cnt_h - (H_BLANK - 1) : 0;
  61. assign y_cnt = (cnt_v >= V_BLANK)? cnt_v - (V_BLANK) : 0;
  62. always @(posedge i_clk_65mhz or posedge i_rst) begin
  63. if (i_rst) begin
  64. rgb_data <= 0;
  65. end
  66. /* else if (x_cnt == h_vo || y_cnt == v_vo) begin
  67. rgb_data <= 24'hff_00_00;
  68. end */
  69. else if (x_cnt == 0 || x_cnt == 639 || x_cnt == 1279) begin
  70. rgb_data <= 24'hff_00_00;
  71. end
  72. else if (y_cnt == 0 || y_cnt == 20 || y_cnt == 40) begin
  73. rgb_data <= 24'hff_00_00;
  74. end
  75. else begin
  76. rgb_data <= 24'hffffff;
  77. end
  78. end
  79. assign {o_red_data, o_gre_data, o_blu_data} = rgb_data;

        4.2 lvds_output_driver详细设计

       第一种写法:

  1. // CLK
  2. OSERDESE2 #(
  3. .DATA_RATE_OQ ("SDR" ), // DDR, SDR
  4. .DATA_RATE_TQ ("SDR" ), // DDR, BUF, SDR
  5. .DATA_WIDTH (7 ), // Parallel data width (2-8,10,14)
  6. .INIT_OQ (1'b0 ), // Initial value of OQ output (1'b0,1'b1)
  7. .INIT_TQ (1'b0 ), // Initial value of TQ output (1'b0,1'b1)
  8. .SERDES_MODE ("MASTER" ), // MASTER, SLAVE
  9. .SRVAL_OQ (1'b0 ), // OQ output value when SR is used (1'b0,1'b1)
  10. .SRVAL_TQ (1'b0 ), // TQ output value when SR is used (1'b0,1'b1)
  11. .TBYTE_CTL ("FALSE" ), // Enable tristate byte operation (FALSE, TRUE)
  12. .TBYTE_SRC ("FALSE" ), // Tristate byte source (FALSE, TRUE)
  13. .TRISTATE_WIDTH (1 ) // 3-state converter width (1,4)
  14. )
  15. OSERDES_clk_inst (
  16. .OFB ( ), // 1-bit output: Feedback path for data
  17. .OQ (oserdes_clk ), // 1-bit output: Data path output
  18. // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
  19. .SHIFTOUT1 ( ),
  20. .SHIFTOUT2 ( ),
  21. .TBYTEOUT ( ), // 1-bit output: Byte group tristate
  22. .TFB ( ), // 1-bit output: 3-state control
  23. .TQ ( ), // 1-bit output: 3-state control
  24. .CLK (i_clk_455mhz ), // 1-bit input: High speed clock
  25. .CLKDIV (i_clk_65mhz ), // 1-bit input: Divided clock
  26. // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
  27. .D1 (CLK_PATTERN[0] ),
  28. .D2 (CLK_PATTERN[1] ),
  29. .D3 (CLK_PATTERN[2] ),
  30. .D4 (CLK_PATTERN[3] ),
  31. .D5 (CLK_PATTERN[4] ),
  32. .D6 (CLK_PATTERN[5] ),
  33. .D7 (CLK_PATTERN[6] ),
  34. .D8 ( ),
  35. .OCE (1'b1 ), // 1-bit input: Output data clock enable
  36. .RST (i_rst ), // 1-bit input: Reset
  37. // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
  38. .SHIFTIN1 (1'b0 ),
  39. .SHIFTIN2 (1'b0 ),
  40. // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
  41. .T1 (1'b0 ),
  42. .T2 (1'b0 ),
  43. .T3 (1'b0 ),
  44. .T4 (1'b0 ),
  45. .TBYTEIN (1'b0 ), // 1-bit input: Byte group tristate
  46. .TCE (1'b0 ) // 1-bit input: 3-state clock enable
  47. );
  48. OBUFDS #(
  49. .IOSTANDARD ("DEFAULT" ), // Specify the output I/O standard
  50. .SLEW ("SLOW" ) // Specify the output slew rate
  51. ) OBUFDS_CLK_inst (
  52. .O (tx_clk_p ), // Diff_p output (connect directly to top-level port)
  53. .OB (tx_clk_n ), // Diff_n output (connect directly to top-level port)
  54. .I (oserdes_clk ) // Buffer input
  55. );
  56. // 1 PAIR
  57. OSERDESE2 #(
  58. .DATA_RATE_OQ ("SDR" ), // DDR, SDR
  59. .DATA_RATE_TQ ("SDR" ), // DDR, BUF, SDR
  60. .DATA_WIDTH (7 ), // Parallel data width (2-8,10,14)
  61. .INIT_OQ (1'b0 ), // Initial value of OQ output (1'b0,1'b1)
  62. .INIT_TQ (1'b0 ), // Initial value of TQ output (1'b0,1'b1)
  63. .SERDES_MODE ("MASTER" ), // MASTER, SLAVE
  64. .SRVAL_OQ (1'b0 ), // OQ output value when SR is used (1'b0,1'b1)
  65. .SRVAL_TQ (1'b0 ), // TQ output value when SR is used (1'b0,1'b1)
  66. .TBYTE_CTL ("FALSE" ), // Enable tristate byte operation (FALSE, TRUE)
  67. .TBYTE_SRC ("FALSE" ), // Tristate byte source (FALSE, TRUE)
  68. .TRISTATE_WIDTH (1 ) // 3-state converter width (1,4)
  69. )
  70. OSERDES_data_inst0 (
  71. .OFB ( ), // 1-bit output: Feedback path for data
  72. .OQ (oserdes_data[0]), // 1-bit output: Data path output
  73. // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
  74. .SHIFTOUT1 ( ),
  75. .SHIFTOUT2 ( ),
  76. .TBYTEOUT ( ), // 1-bit output: Byte group tristate
  77. .TFB ( ), // 1-bit output: 3-state control
  78. .TQ ( ), // 1-bit output: 3-state control
  79. .CLK (i_clk_455mhz ), // 1-bit input: High speed clock
  80. .CLKDIV (i_clk_65mhz ), // 1-bit input: Divided clock
  81. // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
  82. .D1 (i_gre_data[0] ),
  83. .D2 (i_red_data[5] ),
  84. .D3 (i_red_data[4] ),
  85. .D4 (i_red_data[3] ),
  86. .D5 (i_red_data[2] ),
  87. .D6 (i_red_data[1] ),
  88. .D7 (i_red_data[0] ),
  89. .D8 ( ),
  90. .OCE (1'b1 ), // 1-bit input: Output data clock enable
  91. .RST (i_rst ), // 1-bit input: Reset
  92. // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
  93. .SHIFTIN1 (1'b0 ),
  94. .SHIFTIN2 (1'b0 ),
  95. // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
  96. .T1 (1'b0 ),
  97. .T2 (1'b0 ),
  98. .T3 (1'b0 ),
  99. .T4 (1'b0 ),
  100. .TBYTEIN (1'b0 ), // 1-bit input: Byte group tristate
  101. .TCE (1'b0 ) // 1-bit input: 3-state clock enable
  102. );
  103. OBUFDS #(
  104. .IOSTANDARD ("DEFAULT" ), // Specify the output I/O standard
  105. .SLEW ("SLOW" ) // Specify the output slew rate
  106. ) OBUFDS_DATA_inst0 (
  107. .O (lvds_data_p[0] ), // Diff_p output (connect directly to top-level port)
  108. .OB (lvds_data_n[0] ), // Diff_n output (connect directly to top-level port)
  109. .I (oserdes_data[0]) // Buffer input
  110. );
  111. // 2 PAIR
  112. OSERDESE2 #(
  113. .DATA_RATE_OQ ("SDR" ), // DDR, SDR
  114. .DATA_RATE_TQ ("SDR" ), // DDR, BUF, SDR
  115. .DATA_WIDTH (7 ), // Parallel data width (2-8,10,14)
  116. .INIT_OQ (1'b0 ), // Initial value of OQ output (1'b0,1'b1)
  117. .INIT_TQ (1'b0 ), // Initial value of TQ output (1'b0,1'b1)
  118. .SERDES_MODE ("MASTER" ), // MASTER, SLAVE
  119. .SRVAL_OQ (1'b0 ), // OQ output value when SR is used (1'b0,1'b1)
  120. .SRVAL_TQ (1'b0 ), // TQ output value when SR is used (1'b0,1'b1)
  121. .TBYTE_CTL ("FALSE" ), // Enable tristate byte operation (FALSE, TRUE)
  122. .TBYTE_SRC ("FALSE" ), // Tristate byte source (FALSE, TRUE)
  123. .TRISTATE_WIDTH (1 ) // 3-state converter width (1,4)
  124. )
  125. OSERDES_data_inst1 (
  126. .OFB ( ), // 1-bit output: Feedback path for data
  127. .OQ (oserdes_data[1]), // 1-bit output: Data path output
  128. // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
  129. .SHIFTOUT1 ( ),
  130. .SHIFTOUT2 ( ),
  131. .TBYTEOUT ( ), // 1-bit output: Byte group tristate
  132. .TFB ( ), // 1-bit output: 3-state control
  133. .TQ ( ), // 1-bit output: 3-state control
  134. .CLK (i_clk_455mhz ), // 1-bit input: High speed clock
  135. .CLKDIV (i_clk_65mhz ), // 1-bit input: Divided clock
  136. // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
  137. .D1 (i_blu_data[1] ),
  138. .D2 (i_blu_data[0] ),
  139. .D3 (i_gre_data[5] ),
  140. .D4 (i_gre_data[4] ),
  141. .D5 (i_gre_data[3] ),
  142. .D6 (i_gre_data[2] ),
  143. .D7 (i_gre_data[1] ),
  144. .D8 ( ),
  145. .OCE (1'b1 ), // 1-bit input: Output data clock enable
  146. .RST (i_rst ), // 1-bit input: Reset
  147. // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
  148. .SHIFTIN1 (1'b0 ),
  149. .SHIFTIN2 (1'b0 ),
  150. // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
  151. .T1 (1'b0 ),
  152. .T2 (1'b0 ),
  153. .T3 (1'b0 ),
  154. .T4 (1'b0 ),
  155. .TBYTEIN (1'b0 ), // 1-bit input: Byte group tristate
  156. .TCE (1'b0 ) // 1-bit input: 3-state clock enable
  157. );
  158. OBUFDS #(
  159. .IOSTANDARD ("DEFAULT" ), // Specify the output I/O standard
  160. .SLEW ("SLOW" ) // Specify the output slew rate
  161. ) OBUFDS_DATA_inst1 (
  162. .O (lvds_data_p[1] ), // Diff_p output (connect directly to top-level port)
  163. .OB (lvds_data_n[1] ), // Diff_n output (connect directly to top-level port)
  164. .I (oserdes_data[1]) // Buffer input
  165. );
  166. // 3 PAIR
  167. OSERDESE2 #(
  168. .DATA_RATE_OQ ("SDR" ), // DDR, SDR
  169. .DATA_RATE_TQ ("SDR" ), // DDR, BUF, SDR
  170. .DATA_WIDTH (7 ), // Parallel data width (2-8,10,14)
  171. .INIT_OQ (1'b0 ), // Initial value of OQ output (1'b0,1'b1)
  172. .INIT_TQ (1'b0 ), // Initial value of TQ output (1'b0,1'b1)
  173. .SERDES_MODE ("MASTER" ), // MASTER, SLAVE
  174. .SRVAL_OQ (1'b0 ), // OQ output value when SR is used (1'b0,1'b1)
  175. .SRVAL_TQ (1'b0 ), // TQ output value when SR is used (1'b0,1'b1)
  176. .TBYTE_CTL ("FALSE" ), // Enable tristate byte operation (FALSE, TRUE)
  177. .TBYTE_SRC ("FALSE" ), // Tristate byte source (FALSE, TRUE)
  178. .TRISTATE_WIDTH (1 ) // 3-state converter width (1,4)
  179. )
  180. OSERDES_data_inst2 (
  181. .OFB ( ), // 1-bit output: Feedback path for data
  182. .OQ (oserdes_data[2]), // 1-bit output: Data path output
  183. // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
  184. .SHIFTOUT1 ( ),
  185. .SHIFTOUT2 ( ),
  186. .TBYTEOUT ( ), // 1-bit output: Byte group tristate
  187. .TFB ( ), // 1-bit output: 3-state control
  188. .TQ ( ), // 1-bit output: 3-state control
  189. .CLK (i_clk_455mhz ), // 1-bit input: High speed clock
  190. .CLKDIV (i_clk_65mhz ), // 1-bit input: Divided clock
  191. // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
  192. .D1 (i_data_en ),
  193. .D2 (i_v_sync ),
  194. .D3 (i_h_sync ),
  195. .D4 (i_blu_data[5] ),
  196. .D5 (i_blu_data[4] ),
  197. .D6 (i_blu_data[3] ),
  198. .D7 (i_blu_data[2] ),
  199. .D8 ( ),
  200. .OCE (1'b1 ), // 1-bit input: Output data clock enable
  201. .RST (i_rst ), // 1-bit input: Reset
  202. // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
  203. .SHIFTIN1 (1'b0 ),
  204. .SHIFTIN2 (1'b0 ),
  205. // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
  206. .T1 (1'b0 ),
  207. .T2 (1'b0 ),
  208. .T3 (1'b0 ),
  209. .T4 (1'b0 ),
  210. .TBYTEIN (1'b0 ), // 1-bit input: Byte group tristate
  211. .TCE (1'b0 ) // 1-bit input: 3-state clock enable
  212. );
  213. OBUFDS #(
  214. .IOSTANDARD ("DEFAULT" ), // Specify the output I/O standard
  215. .SLEW ("SLOW" ) // Specify the output slew rate
  216. ) OBUFDS_DATA_inst2 (
  217. .O (lvds_data_p[2] ), // Diff_p output (connect directly to top-level port)
  218. .OB (lvds_data_n[2] ), // Diff_n output (connect directly to top-level port)
  219. .I (oserdes_data[2]) // Buffer input
  220. );
  221. // 4 PAIR
  222. OSERDESE2 #(
  223. .DATA_RATE_OQ ("SDR" ), // DDR, SDR
  224. .DATA_RATE_TQ ("SDR" ), // DDR, BUF, SDR
  225. .DATA_WIDTH (7 ), // Parallel data width (2-8,10,14)
  226. .INIT_OQ (1'b0 ), // Initial value of OQ output (1'b0,1'b1)
  227. .INIT_TQ (1'b0 ), // Initial value of TQ output (1'b0,1'b1)
  228. .SERDES_MODE ("MASTER" ), // MASTER, SLAVE
  229. .SRVAL_OQ (1'b0 ), // OQ output value when SR is used (1'b0,1'b1)
  230. .SRVAL_TQ (1'b0 ), // TQ output value when SR is used (1'b0,1'b1)
  231. .TBYTE_CTL ("FALSE" ), // Enable tristate byte operation (FALSE, TRUE)
  232. .TBYTE_SRC ("FALSE" ), // Tristate byte source (FALSE, TRUE)
  233. .TRISTATE_WIDTH (1 ) // 3-state converter width (1,4)
  234. )
  235. OSERDES_data_inst3 (
  236. .OFB ( ), // 1-bit output: Feedback path for data
  237. .OQ (oserdes_data[3]), // 1-bit output: Data path output
  238. // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
  239. .SHIFTOUT1 ( ),
  240. .SHIFTOUT2 ( ),
  241. .TBYTEOUT ( ), // 1-bit output: Byte group tristate
  242. .TFB ( ), // 1-bit output: 3-state control
  243. .TQ ( ), // 1-bit output: 3-state control
  244. .CLK (i_clk_455mhz ), // 1-bit input: High speed clock
  245. .CLKDIV (i_clk_65mhz ), // 1-bit input: Divided clock
  246. // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
  247. .D1 (DON_CR ),
  248. .D2 (i_blu_data[7] ),
  249. .D3 (i_blu_data[6] ),
  250. .D4 (i_gre_data[7] ),
  251. .D5 (i_gre_data[6] ),
  252. .D6 (i_red_data[7] ),
  253. .D7 (i_red_data[6] ),
  254. .D8 ( ),
  255. .OCE (1'b1 ), // 1-bit input: Output data clock enable
  256. .RST (i_rst ), // 1-bit input: Reset
  257. // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
  258. .SHIFTIN1 (1'b0 ),
  259. .SHIFTIN2 (1'b0 ),
  260. // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
  261. .T1 (1'b0 ),
  262. .T2 (1'b0 ),
  263. .T3 (1'b0 ),
  264. .T4 (1'b0 ),
  265. .TBYTEIN (1'b0 ), // 1-bit input: Byte group tristate
  266. .TCE (1'b0 ) // 1-bit input: 3-state clock enable
  267. );
  268. OBUFDS #(
  269. .IOSTANDARD ("DEFAULT" ), // Specify the output I/O standard
  270. .SLEW ("SLOW" ) // Specify the output slew rate
  271. ) OBUFDS_DATA_inst3 (
  272. .O (lvds_data_p[3] ), // Diff_p output (connect directly to top-level port)
  273. .OB (lvds_data_n[3] ), // Diff_n output (connect directly to top-level port)
  274. .I (oserdes_data[3]) // Buffer input
  275. );

        第二种写法,采用generate语句:

  1. parameter DON_CR = 0;
  2. parameter CLK_PATTERN = 7'b11_000_11;
  3. wire [23:0] din;
  4. wire oserdes_clk ; // oserdes output clk
  5. wire [3:0] oserdes_data; // oserdes output data
  6. genvar i;
  7. assign din = { DON_CR, i_blu_data[7:6], i_gre_data[7:6], i_red_data[7:6],
  8. i_data_en, i_v_sync ,i_h_sync, i_blu_data[5:2],
  9. i_blu_data[1:0], i_gre_data[5:1],
  10. i_gre_data[0], i_red_data[5:0]};
  11. // CLK
  12. OSERDESE2 #(
  13. .DATA_RATE_OQ ("SDR" ), // DDR, SDR
  14. .DATA_RATE_TQ ("SDR" ), // DDR, BUF, SDR
  15. .DATA_WIDTH (7 ), // Parallel data width (2-8,10,14)
  16. .INIT_OQ (1'b0 ), // Initial value of OQ output (1'b0,1'b1)
  17. .INIT_TQ (1'b0 ), // Initial value of TQ output (1'b0,1'b1)
  18. .SERDES_MODE ("MASTER" ), // MASTER, SLAVE
  19. .SRVAL_OQ (1'b0 ), // OQ output value when SR is used (1'b0,1'b1)
  20. .SRVAL_TQ (1'b0 ), // TQ output value when SR is used (1'b0,1'b1)
  21. .TBYTE_CTL ("FALSE" ), // Enable tristate byte operation (FALSE, TRUE)
  22. .TBYTE_SRC ("FALSE" ), // Tristate byte source (FALSE, TRUE)
  23. .TRISTATE_WIDTH (1 ) // 3-state converter width (1,4)
  24. )
  25. OSERDES_clk_inst (
  26. .OFB ( ), // 1-bit output: Feedback path for data
  27. .OQ (oserdes_clk ), // 1-bit output: Data path output
  28. // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
  29. .SHIFTOUT1 ( ),
  30. .SHIFTOUT2 ( ),
  31. .TBYTEOUT ( ), // 1-bit output: Byte group tristate
  32. .TFB ( ), // 1-bit output: 3-state control
  33. .TQ ( ), // 1-bit output: 3-state control
  34. .CLK (i_clk_455mhz ), // 1-bit input: High speed clock
  35. .CLKDIV (i_clk_65mhz ), // 1-bit input: Divided clock
  36. // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
  37. .D1 (CLK_PATTERN[0] ),
  38. .D2 (CLK_PATTERN[1] ),
  39. .D3 (CLK_PATTERN[2] ),
  40. .D4 (CLK_PATTERN[3] ),
  41. .D5 (CLK_PATTERN[4] ),
  42. .D6 (CLK_PATTERN[5] ),
  43. .D7 (CLK_PATTERN[6] ),
  44. .D8 ( ),
  45. .OCE (1'b1 ), // 1-bit input: Output data clock enable
  46. .RST (i_rst ), // 1-bit input: Reset
  47. // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
  48. .SHIFTIN1 (1'b0 ),
  49. .SHIFTIN2 (1'b0 ),
  50. // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
  51. .T1 (1'b0 ),
  52. .T2 (1'b0 ),
  53. .T3 (1'b0 ),
  54. .T4 (1'b0 ),
  55. .TBYTEIN (1'b0 ), // 1-bit input: Byte group tristate
  56. .TCE (1'b0 ) // 1-bit input: 3-state clock enable
  57. );
  58. OBUFDS #(
  59. .IOSTANDARD ("DEFAULT" ), // Specify the output I/O standard
  60. .SLEW ("SLOW" ) // Specify the output slew rate
  61. ) OBUFDS_CLK_inst (
  62. .O (o_tx_clk_p ), // Diff_p output (connect directly to top-level port)
  63. .OB (o_tx_clk_n ), // Diff_n output (connect directly to top-level port)
  64. .I (oserdes_clk ) // Buffer input
  65. );
  66. // DATA
  67. generate
  68. for (i = 0; i<4; i=i+1) begin
  69. OSERDESE2 #(
  70. .DATA_RATE_OQ ("SDR" ), // DDR, SDR
  71. .DATA_RATE_TQ ("SDR" ), // DDR, BUF, SDR
  72. .DATA_WIDTH (7 ), // Parallel data width (2-8,10,14)
  73. .INIT_OQ (1'b0 ), // Initial value of OQ output (1'b0,1'b1)
  74. .INIT_TQ (1'b0 ), // Initial value of TQ output (1'b0,1'b1)
  75. .SERDES_MODE ("MASTER" ), // MASTER, SLAVE
  76. .SRVAL_OQ (1'b0 ), // OQ output value when SR is used (1'b0,1'b1)
  77. .SRVAL_TQ (1'b0 ), // TQ output value when SR is used (1'b0,1'b1)
  78. .TBYTE_CTL ("FALSE" ), // Enable tristate byte operation (FALSE, TRUE)
  79. .TBYTE_SRC ("FALSE" ), // Tristate byte source (FALSE, TRUE)
  80. .TRISTATE_WIDTH (1 ) // 3-state converter width (1,4)
  81. )
  82. OSERDES_data_inst0 (
  83. .OFB ( ), // 1-bit output: Feedback path for data
  84. .OQ (oserdes_data[i]), // 1-bit output: Data path output
  85. // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
  86. .SHIFTOUT1 ( ),
  87. .SHIFTOUT2 ( ),
  88. .TBYTEOUT ( ), // 1-bit output: Byte group tristate
  89. .TFB ( ), // 1-bit output: 3-state control
  90. .TQ ( ), // 1-bit output: 3-state control
  91. .CLK (i_clk_455mhz ), // 1-bit input: High speed clock
  92. .CLKDIV (i_clk_65mhz ), // 1-bit input: Divided clock
  93. // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
  94. .D1 (i_gre_data[i*8+6]),
  95. .D2 (i_red_data[i*8+5]),
  96. .D3 (i_red_data[i*8+4]),
  97. .D4 (i_red_data[i*8+3]),
  98. .D5 (i_red_data[i*8+2]),
  99. .D6 (i_red_data[i*8+1]),
  100. .D7 (i_red_data[i*8+0]),
  101. .D8 ( ),
  102. .OCE (1'b1 ), // 1-bit input: Output data clock enable
  103. .RST (i_rst ), // 1-bit input: Reset
  104. // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
  105. .SHIFTIN1 (1'b0 ),
  106. .SHIFTIN2 (1'b0 ),
  107. // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
  108. .T1 (1'b0 ),
  109. .T2 (1'b0 ),
  110. .T3 (1'b0 ),
  111. .T4 (1'b0 ),
  112. .TBYTEIN (1'b0 ), // 1-bit input: Byte group tristate
  113. .TCE (1'b0 ) // 1-bit input: 3-state clock enable
  114. );
  115. OBUFDS #(
  116. .IOSTANDARD ("DEFAULT" ), // Specify the output I/O standard
  117. .SLEW ("SLOW" ) // Specify the output slew rate
  118. ) OBUFDS_DATA_inst0 (
  119. .O (o_lvds_data_p[i]), // Diff_p output (connect directly to top-level port)
  120. .OB (o_lvds_data_n[i]), // Diff_n output (connect directly to top-level port)
  121. .I (oserdes_data[i] ) // Buffer input
  122. );
  123. end
  124. endgenerate

        4.3 顶层设计

  1. module a_top (
  2. input clk , // sys_clk
  3. output pwm_pannel , // backlight
  4. output o_tx_clk_p ,
  5. output o_tx_clk_n ,
  6. output [3:0] lvds_data_p ,
  7. output [3:0] lvds_data_n
  8. );
  9. wire clk_65mhz ;
  10. wire clk_455mhz ;
  11. wire rst ;
  12. wire [7:0] red_data ;
  13. wire [7:0] gre_data ;
  14. wire [7:0] blu_data ;
  15. wire h_sync ;
  16. wire v_sync ;
  17. wire data_en ;
  18. assign pwm_pannel = 1;
  19. // MMCM
  20. clk_wiz_0 u_clk_wiz_0(
  21. /* output */ .clk_out1 (clk_65mhz ),
  22. /* output */ .clk_out2 (clk_455mhz ),
  23. /* output */ .locked (rst ),
  24. /* input */ .clk_in1 (clk )
  25. );
  26. data_generator u_data_generator(
  27. /* input */ .i_clk_65mhz (clk_65mhz ), //input 65MHz clk, period : 15.38ns
  28. /* input */ .i_rst (!rst ),
  29. /* output [7:0] */ .o_red_data (red_data ),
  30. /* output [7:0] */ .o_gre_data (gre_data ),
  31. /* output [7:0] */ .o_blu_data (blu_data ),
  32. /* output reg */ .o_h_sync (h_sync ),
  33. /* output reg */ .o_v_sync (v_sync ),
  34. /* output reg */ .o_data_en (data_en )
  35. );
  36. lvds_output_driver u_lvds_output_driver(
  37. /* input */ .i_clk_455mhz (clk_455mhz ),
  38. /* input */ .i_clk_65mhz (clk_65mhz ),
  39. /* input */ .i_rst (!rst ),
  40. /* input [7:0] */ .i_red_data (red_data ),
  41. /* input [7:0] */ .i_gre_data (gre_data ),
  42. /* input [7:0] */ .i_blu_data (blu_data ),
  43. /* input */ .i_v_sync (v_sync ),
  44. /* input */ .i_h_sync (h_sync ),
  45. /* input */ .i_data_en (data_en ),
  46. /* output */ .tx_clk_p (o_tx_clk_p ),
  47. /* output */ .tx_clk_n (o_tx_clk_n ),
  48. /* output [3:0] */ .lvds_data_p (lvds_data_p),
  49. /* output [3:0] */ .lvds_data_n (lvds_data_n)
  50. );
  51. endmodule //a_top

5 实现效果

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