【Vivado那些事】vivado生成.bit文件时报错-ERROR: [Drc 23-20]

错误

描述

ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. Problem ports: clk, din, dout.

ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 3 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: clk, din, dout.

原因分析

该错误消息是为了通知客户他们需要设置IOSTANDARD和PACKAGE_PIN，以保护设备免受意外损坏，这可能是由于工具在不了解电路板电压或连接的情况下随机选择了引脚位置或IOSTANDARD而引起的。

例如：

• 如果引脚在板上接地，并且Vivado选择此引脚作为高电平驱动的输出，则会引起竞争。

• 如果板上有一个针对该引脚的端接方案，即HSTL或SSTL建议的端接，并且Vivado选择LVCMOS18（默认值），则信号的信号完整性将达不到最佳状态。

7系列的默认I / O标准是LVCMOS18，用于all banks的单端信号。在以前的体系结构中，默认的I / O标准为LVCMOS25。

解决方案

1.（推荐）为设计中的所有I / O添加IOSTANDARD和PACKAGE_PIN约束。

2.如果您不关心那些不受限制的I / O，请使用以下解决方案之一。

• 对于GUI项目流程，创建一个.tcl文件并放两个命令。在“比特流设置”的“ tcl.pre”选项中指定此.tcl文件。然后，可以重新运行“ Generate Bitstream”（生成比特流），而无需重新运行Implementation。

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

可以将以下命令添加到XDC并重新运行Implementation。

set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]

3.如果您只需要从现有的完成的Implementation运行中生成位文件，并暂时忽略那些不受约束的I / O，请使用以下解决方案：

• 打开已实现的设计或打开路由的DCP，然后在Tcl控制台中运行以下命令：

set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

write_bitstream <path_and_file_name>.bit

或者

set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]

write_bitstream <path_and_file_name>.bit

总结

建议使用解决方案二中方式。

参考资料

1、https://www.xilinx.com/support/answers/56354.html

2、https://www.xilinx.com/support/answers/63125.html

3、https://www.xilinx.com/support/answers/59742.html