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ADC + 数码管显示

作者：正经夜光杯 | 2024-06-28 20:44:15

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ADC + 数码管显示

REVIEW

前面已经学习过：

ADC：ADC模-数转换原理与实现-CSDN博客

key：基于状态机的按键消抖实现-CSDN博客

数码管：SPI接口的74HC595驱动数码管实现_用spi和hc74595通信-CSDN博客

1.  今日摸鱼计划

按键启动ADC

将结果显示在数码管上

2.  key + ADC

key.v

  1. module key_one(
  2.                  input clk , 
  3.                  input reset_n,
  4.                  input key,
  5.                  output reg key_flag,
  6.                  output reg key_state
  7.                  );
  8.            
  9.                  
  10.         // nedge_key pedge_key
  11.         reg dff_k_0 , dff_k_1 ;
  12.         reg r_key; 
  13.         wire  nedge_key, pedge_key;
  14.         always@(posedge clk )    
  15.             dff_k_0 <= key ;
  16.         always@(posedge clk )    
  17.             dff_k_1 <= dff_k_0 ;
  18.         always@(posedge clk )    
  19.             r_key <= dff_k_1 ;
  20.             
  21.         assign nedge_key = (r_key == 1)&&(dff_k_1 == 0);
  22.         assign pedge_key = (r_key == 0)&&(dff_k_1 == 1);
  23.    
  24.         // key_now   0:IDLE   1:FILTER0   2:DOWN   3:FILTER1
  25.         // cnt 20ms/20ns = 1000000 ;
  26.         reg [1:0]key_now;
  27.         reg [19:0] cnt;
  28.         parameter cnt_N = 1000;   //测试使用
  29.         always@(posedge clk or negedge reset_n ) 
  30.             if(!reset_n) 
  31.                 begin
  32.                     key_now <= 0 ;
  33.                     cnt <= 0;
  34.                     key_flag <= 0;
  35.                     key_state <= 1;
  36.                 end
  37.             else 
  38.                 begin
  39.                     key_flag <= 0;
  40.                     case(key_now)
  41.                         0:
  42.                            if(!nedge_key) key_now <= 0;
  43.                            else 
  44.                                begin 
  45.                                  cnt <= 0 ;
  46.                                  key_now <= 1; 
  47.                                end
  48.                                
  49.                         1:
  50.                             if(pedge_key) key_now <= 0;
  51.                             else if(cnt >= cnt_N - 1) 
  52.                                 begin
  53.                                     cnt <= 0 ;
  54.                                     key_now <= 2;
  55.                                     key_flag <= 1;
  56.                                     key_state <= 0;
  57.                                 end
  58.                             else cnt <= cnt + 1'b1;
  59.                             
  60.                         2:
  61.                             if(!pedge_key) key_now <= 2;
  62.                             else
  63.                                 begin
  64.                                     cnt <= 0 ;
  65.                                     key_now <= 3;
  66.                                 end
  67.                         
  68.                         3:
  69.                             if(nedge_key) key_now <= 2;
  70.                             else if(cnt >= cnt_N - 1)
  71.                                  begin
  72.                                     cnt <= 0 ;
  73.                                     key_now <= 0;
  74.                                     key_flag <= 1;
  75.                                     key_state <= 1;
  76.                                 end
  77.                             else cnt <= cnt + 1'b1;    
  78.                         
  79.                     endcase
  80.                 end
  81.  
  82. endmodule

adc128s102.v

  1. module adc128s102(
  2.                 input clk,
  3.                 input reset_n,
  4.                 
  5.                 input Conv_Go,//使能信号
  6.                 input [2:0]Addr,
  7.                 
  8.                 input ADC_DOUT,
  9.                 output reg ADC_SCLK,
  10.                 output reg ADC_CS_N,
  11.                 output reg ADC_DIN,
  12.                 
  13.                 output reg Conv_Done,
  14.                 output reg[11:0]Data
  15.                 );
  16.  
  17.     parameter CLOCK_FREQ = 50_000_000;
  18.     parameter SCLK_FREQ = 12_500_000;
  19.     parameter MCNT_DIV_CNT = CLOCK_FREQ/(SCLK_FREQ * 2) - 1;
  20.  
  21.     reg[7:0]DIV_CNT;
  22.     reg [5:0]LSM_CNT;
  23.     reg [11:0]Data_r;
  24.     reg [2:0]r_Addr;
  25.     
  26.     always@(posedge clk)
  27.     if(Conv_Go)    
  28.         r_Addr <= Addr;
  29.     else
  30.         r_Addr <= r_Addr;
  31.     
  32.     reg Conv_En; //转换使能
  33.     
  34.     always@(posedge clk or negedge reset_n )
  35.     if(!reset_n )
  36.         Conv_En <= 1'd0;
  37.     else if(Conv_Go)
  38.         Conv_En <= 1'd1;
  39.     else if((LSM_CNT == 6'd34) && (DIV_CNT == MCNT_DIV_CNT))
  40.         Conv_En <= 1'd0;
  41.     else
  42.         Conv_En <= Conv_En;
  43.     
  44.     always@(posedge clk or negedge reset_n)
  45.     if(!reset_n)
  46.         DIV_CNT <= 0;
  47.     else if(Conv_En)
  48.         begin
  49.             if(DIV_CNT == MCNT_DIV_CNT)
  50.                 DIV_CNT <= 0;
  51.             else    
  52.                 DIV_CNT <= DIV_CNT + 1'd1;
  53.         end
  54.     else
  55.         DIV_CNT <= 0;
  57.     always@(posedge clk or negedge reset_n)
  58.     if(!reset_n)
  59.         LSM_CNT <= 6'd0;
  60.     else if(DIV_CNT == MCNT_DIV_CNT)
  61.         begin
  62.             if(LSM_CNT == 6'd34)
  63.                 LSM_CNT <= 6'd0;
  64.             else
  65.                 LSM_CNT <= LSM_CNT + 1'd1; 
  66.         end
  67.     else
  68.         LSM_CNT <= LSM_CNT;
  71.     always@(posedge clk or negedge reset_n )
  72.     if(!reset_n )begin
  73.         Data_r <= 12'd0;
  74.         ADC_SCLK <= 1'd1;
  75.         ADC_DIN <= 1'd1;
  76.         ADC_CS_N <= 1'd1;
  77.     end
  78.     else if(DIV_CNT == MCNT_DIV_CNT)begin
  79.         case(LSM_CNT)
  80.             0 : begin ADC_CS_N <= 1'd1; ADC_SCLK <= 1'd1;end
  81.             1 : begin ADC_CS_N <= 1'd0;end
  82.             2 : begin ADC_SCLK <= 1'd0;end
  83.             3 : begin ADC_SCLK <= 1'd1;end
  84.             4 : begin ADC_SCLK <= 1'd0;end
  85.             5 : begin ADC_SCLK <= 1'd1;end    
  86.             6 : begin ADC_SCLK <= 1'd0;ADC_DIN <= r_Addr[2]; end
  87.             7 : begin ADC_SCLK <= 1'd1;end    
  88.             8 : begin ADC_SCLK <= 1'd0;ADC_DIN <= r_Addr[1]; end
  89.             9 : begin ADC_SCLK <= 1'd1;end    
  90.             10 :begin ADC_SCLK <= 1'd0;ADC_DIN <= r_Addr[0]; end
  91.             11: begin ADC_SCLK <= 1'd1;Data_r[11] <= ADC_DOUT; end
  92.             12: begin ADC_SCLK <= 1'd0;ADC_DIN <= 1'd1;end
  93.                                         //这里跟之前有一点不一样，将ADC_DIN <= 1'd1;
  94.             13: begin ADC_SCLK <= 1'd1;Data_r[10] <= ADC_DOUT; end
  95.             14: begin ADC_SCLK <= 1'd0;end    
  96.             15: begin ADC_SCLK <= 1'd1;Data_r[9] <= ADC_DOUT; end
  97.             16: begin ADC_SCLK <= 1'd0;end
  98.             17: begin ADC_SCLK <= 1'd1;Data_r[8] <= ADC_DOUT; end
  99.             18: begin ADC_SCLK <= 1'd0;end    
  100.             19: begin ADC_SCLK <= 1'd1;Data_r[7] <= ADC_DOUT; end
  101.             20: begin ADC_SCLK <= 1'd0;end
  102.             21: begin ADC_SCLK <= 1'd1;Data_r[6] <= ADC_DOUT; end
  103.             22: begin ADC_SCLK <= 1'd0;end    
  104.             23: begin ADC_SCLK <= 1'd1;Data_r[5] <= ADC_DOUT; end
  105.             24: begin ADC_SCLK <= 1'd0;end
  106.             25: begin ADC_SCLK <= 1'd1;Data_r[4] <= ADC_DOUT; end
  107.             26: begin ADC_SCLK <= 1'd0;end    
  108.             27: begin ADC_SCLK <= 1'd1;Data_r[3] <= ADC_DOUT; end
  109.             28: begin ADC_SCLK <= 1'd0;end
  110.             29: begin ADC_SCLK <= 1'd1;Data_r[2] <= ADC_DOUT; end
  111.             30: begin ADC_SCLK <= 1'd0;end    
  112.             31: begin ADC_SCLK <= 1'd1;Data_r[1] <= ADC_DOUT; end
  113.             32: begin ADC_SCLK <= 1'd0;end
  114.             33: begin ADC_SCLK <= 1'd1;Data_r[0] <= ADC_DOUT; end
  115.             34: begin ADC_SCLK <= 1'd1;ADC_CS_N <= 1'd1; end
  116.             default: ADC_CS_N <= 1'd1; 
  117.         endcase
  118.     end
  120.     always@(posedge clk or negedge reset_n )
  121.     if(!reset_n )
  122.         begin
  123.             Data <= 12'd0;
  124.             Conv_Done <= 0;
  125.         end
  126.     else if((LSM_CNT == 34) && (DIV_CNT == MCNT_DIV_CNT))
  127.         begin
  128.             Conv_Done <= 1'd1;
  129.             Data <= Data_r;
  130.         end
  131.     else 
  132.         begin
  133.             Conv_Done <= 1'd0;
  134.             Data <= Data;
  135.         end
  136.  
  137. endmodule

key_adc.v

  1.  
  2. module key_adc(
  3.                  input clk , 
  4.                  input reset_n,
  5.                  input key,
  6.                  
  7.                  input [2:0]Addr,
  8.                  input ADC_DOUT,
  9.                  output  ADC_SCLK,
  10.                  output  ADC_CS_N,
  11.                  output  ADC_DIN,
  12.                 
  13.                  output  Conv_Done,
  14.                  output [11:0]Data
  15.                     );
  16.                     
  17.                     
  18.      wire key_flag , key_state ;               
  19.      key_one key_one_(
  20.                      . clk(clk) , 
  21.                      . reset_n(reset_n),
  22.                      . key(key),
  23.                      . key_flag(key_flag),
  24.                      . key_state(key_state)
  25.                      );     
  26.                      
  27.                                
  28.      reg  Conv_Go ;  
  29.      always@(posedge clk or negedge reset_n )
  30.      if(!reset_n ) 
  31.         Conv_Go <= 1'b0 ;
  32.      else if((key_flag)&&(key_state==1))
  33.                     //(key_flag)&&(key_state==1)代表按键按下后松开
  34.                     //之前都是按下作为判定，本次有一点不同
  35.         Conv_Go <= 1'b1 ;
  36.      else
  37.         Conv_Go <= 1'b0 ;
  38.         
  39.      adc128s102 adc_(
  40.                 . clk(clk),
  41.                 . reset_n(reset_n),
  42.                 
  43.                 . Conv_Go(Conv_Go),//使能信号
  44.                 . Addr(Addr),
  45.                 
  46.                 . ADC_DOUT(ADC_DOUT),
  47.                 . ADC_SCLK(ADC_SCLK),
  48.                 . ADC_CS_N(ADC_CS_N),
  49.                 . ADC_DIN(ADC_DIN),
  50.                 
  51.                 . Conv_Done(Conv_Done),
  52.                 . Data(Data)
  53.                 );   
  54.         
  55.         
  56.         
  57.                     
  58.                     
  59. endmodule

key_adc_tb.v

  1. `timescale 1ns / 1ns
  2.  
  3. module key_adc_tb(    );
  4.  
  5.         reg clk;
  6.         reg reset_n;
  7.         reg key ;
  8.         reg [2:0]Addr;
  9.         reg ADC_DOUT;
  10.         wire ADC_SCLK;
  11.         wire ADC_CS_N;
  12.         wire ADC_DIN;
  13.         wire Conv_Done;
  14.         wire[11:0]Data;
  15.  
  16.         
  17.        key_adc key_adc_(
  18.                          . clk(clk) , 
  19.                          . reset_n(reset_n),
  20.                          . key(key),
  21.                          
  22.                          . Addr(Addr),
  23.                         
  24.                          . ADC_DOUT(ADC_DOUT),
  25.                          . ADC_SCLK(ADC_SCLK),
  26.                          . ADC_CS_N(ADC_CS_N),
  27.                          . ADC_DIN(ADC_DIN),
  28.                         
  29.                         . Conv_Done(Conv_Done),
  30.                         . Data(Data)
  31.                     );
  32.         
  33.         initial clk = 1;
  34.         always #10 clk = ~clk;
  35.         
  36.          initial 
  37.     begin
  38.         reset_n = 0;
  39.         Addr = 2;
  40.         key = 1 ;
  41.         #201;
  42.         reset_n = 1;
  43.         #200;
  44.         key_press(2);
  45.          
  46.         wait(!ADC_CS_N);
  47.         //16'h0A58
  48.         @(negedge ADC_SCLK);
  49.         ADC_DOUT = 0; //DB15 
  50.         @(negedge ADC_SCLK);
  51.         ADC_DOUT = 0; //DB14 
  52.         @(negedge ADC_SCLK);
  53.         ADC_DOUT = 0; //DB13        
  54.         @(negedge ADC_SCLK);
  55.         ADC_DOUT = 0; //DB12        
  56.         @(negedge ADC_SCLK);
  57.         ADC_DOUT = 1; //DB11          
  58.         @(negedge ADC_SCLK);
  59.         ADC_DOUT = 0; //DB10         
  60.         @(negedge ADC_SCLK);
  61.         ADC_DOUT = 1; //DB9         
  62.         @(negedge ADC_SCLK);
  63.         ADC_DOUT = 0; //DB8         
  64.         @(negedge ADC_SCLK);
  65.         ADC_DOUT = 0; //DB7         
  66.         @(negedge ADC_SCLK);
  67.         ADC_DOUT = 1; //DB6         
  68.         @(negedge ADC_SCLK);
  69.         ADC_DOUT = 0; //DB5         
  70.         @(negedge ADC_SCLK);
  71.         ADC_DOUT = 1; //DB4        
  72.         @(negedge ADC_SCLK);
  73.         ADC_DOUT = 1; //DB3         
  74.         @(negedge ADC_SCLK);
  75.         ADC_DOUT = 0; //DB2        
  76.         @(negedge ADC_SCLK);
  77.         ADC_DOUT = 0; //DB1         
  78.         @(negedge ADC_SCLK);
  79.         ADC_DOUT = 0; //DB0      
  80.         wait(ADC_CS_N);
  81.         #2000;   
  82.              
  83.         
  84.         Addr = 7;
  85.         #20;
  86.       key_press(2);     
  87.         wait(!ADC_CS_N);
  88.         //16'h0893
  89.         @(negedge ADC_SCLK);
  90.         ADC_DOUT = 0;
  91.         @(negedge ADC_SCLK);
  92.         ADC_DOUT = 0;
  93.         @(negedge ADC_SCLK);
  94.         ADC_DOUT = 0;        
  95.         @(negedge ADC_SCLK);
  96.         ADC_DOUT = 0;        
  97.         @(negedge ADC_SCLK);
  98.         ADC_DOUT = 1;          
  99.         @(negedge ADC_SCLK);
  100.         ADC_DOUT = 0;         
  101.         @(negedge ADC_SCLK);
  102.         ADC_DOUT = 0;         
  103.         @(negedge ADC_SCLK);
  104.         ADC_DOUT = 0;         
  105.         @(negedge ADC_SCLK);
  106.         ADC_DOUT = 1;         
  107.         @(negedge ADC_SCLK);
  108.         ADC_DOUT = 0;         
  109.         @(negedge ADC_SCLK);
  110.         ADC_DOUT = 0;         
  111.         @(negedge ADC_SCLK);
  112.         ADC_DOUT = 1;         
  113.         @(negedge ADC_SCLK);
  114.         ADC_DOUT = 0;         
  115.         @(negedge ADC_SCLK);
  116.         ADC_DOUT = 0;         
  117.         @(negedge ADC_SCLK);
  118.         ADC_DOUT = 1;         
  119.         @(negedge ADC_SCLK);
  120.         ADC_DOUT = 1;       
  121.         wait(ADC_CS_N);
  122.         #200;    
  123.         #100000;
  124.  
  125.         $stop;
  126.     end
  127.  
  128. reg [13:0] rand;
  129.  task key_press;
  130.     input[3:0]seed;
  131.     begin
  132.         key =  1 ;
  133.         #100000;
  134.         repeat(10)
  135.             begin
  136.                 rand = {$random(seed)} % 10000;
  137.                 #rand;
  138.                 key=~key;
  139.             end
  140.         key = 0 ;
  141.         #100000;
  142.          key =  1 ;
  143.     end 
  144. endtask      
  145.         
  146.         
  147. endmodule

分析

adc中做了这样一个小改动，没什么别的作用，这个就是摸鱼怪觉得看起来好看一点。

关于按键的判断，这里是因为在调试按键按下后，发现wait等不到CS下降沿信号，从而DOUT未触发。

测试结果如下：

经过分析，测试文件一直走不到 wait(!ADC_CS_N);

是因为!ADC_CS_N 在 key_press(2);结束之前已经发生了

因此为了测试分析，本次选择使用按键松开为判定

注意：本次测试为了可以 wait(!ADC_CS_N);

按键松开后，不要停留过长时间！

此时看以看出，进行了两次正常的读取。

3.  key + ADC + 数码管

hex_8.v

  1. module hex_8(
  2.              input clk,
  3.              input reset_n,
  4.              input [31:0]disp_data,
  5.              output reg [7:0]sel,
  6.              output reg [7:0]seg
  7.              );
  8.  
  9. //[31:0]disp_data  16hex 4*8
  10. //[7:0]sel 位选信号
  11. //[7:0]seg 段选信号
  12.  
  13. // 1kHz分频时钟 
  14.     reg [14:0]div_clk;
  15.     always@(posedge clk or negedge reset_n)
  16.     if(!reset_n) 
  17.         div_clk <= 1'b0;
  18.     else if(div_clk == 24999) 
  19.         div_clk <= 1'b0;
  20.     else 
  21.         div_clk <= div_clk + 1'b1;
  22.     reg disp_en;
  23.    always@(posedge clk or negedge reset_n)
  24.     if(!reset_n) 
  25.         disp_en <= 1'b0;
  26.     else if(div_clk == 24999) 
  27.         disp_en <= 1'b1;
  28.     else 
  29.         disp_en <= 1'b0;    
  30.  
  31. //  位选sel
  32.     reg[2:0]sel_num;
  33.     always@(posedge clk or negedge reset_n)
  34.     if(!reset_n) 
  35.         sel_num <= 3'b000;
  36.     else if(disp_en) 
  37.         sel_num <= sel_num + 1'b1;
  38.         
  39.     always@(posedge clk or negedge reset_n)
  40.     if(!reset_n) 
  41.         sel <= 8'b0000_0000;
  42.     else case(sel_num) 
  43.          0:sel <= 8'b0000_0001;
  44.          1:sel <= 8'b0000_0010;
  45.          2:sel <= 8'b0000_0100;
  46.          3:sel <= 8'b0000_1000;
  47.          4:sel <= 8'b0001_0000;
  48.          5:sel <= 8'b0010_0000;
  49.          6:sel <= 8'b0100_0000;
  50.          7:sel <= 8'b1000_0000;
  51.     endcase   
  52.    
  53. // 段选seg   [31:0]disp_data  16hex 4*8
  54.     reg [3:0] dis_tmp;
  55.     always@(posedge clk )
  56.     case(sel_num) //高位放前面
  57.          7:dis_tmp <= disp_data[31:28];
  58.          6:dis_tmp <= disp_data[27:24];
  59.          5:dis_tmp <= disp_data[23:20];
  60.          4:dis_tmp <= disp_data[19:16];
  61.          3:dis_tmp <= disp_data[15:12];
  62.          2:dis_tmp <= disp_data[11:8];
  63.          1:dis_tmp <= disp_data[7:4];
  64.          0:dis_tmp <= disp_data[3:0];
  65.     endcase 
  66.     
  67.     always@(posedge clk )
  68.     case(dis_tmp) 
  69.          0:seg <= 8'hc0;
  70.          1:seg <= 8'hf9;
  71.          2:seg <= 8'ha4;
  72.          3:seg <= 8'hb0;
  73.          4:seg <= 8'h99;
  74.          5:seg <= 8'h92;
  75.          6:seg <= 8'h82;
  76.          7:seg <= 8'hf8;
  77.          8:seg <= 8'h80;
  78.          9:seg <= 8'h90;
  79.          4'ha:seg <= 8'h88;
  80.          4'hb:seg <= 8'h83;
  81.          4'hc:seg <= 8'hc6;
  82.          4'hd:seg <= 8'ha1;
  83.          4'he:seg <= 8'h86;
  84.          4'hf:seg <= 8'h8e;
  85.     endcase 
  87. endmodule

hc595_driver.v

  1. module hc595_driver(
  2.                         input clk,
  3.                         input reset_n,
  4.                         input [15:0]data ,
  5.                         input s_en ,
  6.                         output reg sh_cp ,
  7.                         output reg st_cp ,
  8.                         output reg ds
  9.                         );
  10.         //接收到s_en才改变r_data                
  11.         reg [15:0]r_data;
  12.         always@(posedge clk)
  13.         if(s_en)
  14.           r_data <= data;
  15.           
  16.         //分频计数器;  
  17.         parameter CNT_MAX = 2; 
  18.         reg [7:0]divider_cnt;
  19.         always@(posedge clk or negedge reset_n)
  20.         if(!reset_n)
  21.             divider_cnt <= 0;
  22.         else if(divider_cnt == CNT_MAX - 1'b1)
  23.             divider_cnt <= 0;
  24.         else
  25.             divider_cnt <= divider_cnt + 1'b1; 
  26.         
  27.         
  28.         wire sck_plus;
  29.     assign sck_plus = (divider_cnt == CNT_MAX - 1'b1);
  30.         
  31.     reg [5:0]SHCP_EDGE_CNT;
  32.     
  33.     always@(posedge clk or negedge reset_n)
  34.     if(!reset_n)
  35.         SHCP_EDGE_CNT <= 0;
  36.     else if(sck_plus)
  37.         begin
  38.             if(SHCP_EDGE_CNT == 6'd32)
  39.                 SHCP_EDGE_CNT <= 0;
  40.             else
  41.                 SHCP_EDGE_CNT <= SHCP_EDGE_CNT + 1'b1;
  42.         end
  43.     else
  44.         SHCP_EDGE_CNT <= SHCP_EDGE_CNT;
  45.         
  46.     always@(posedge clk or negedge reset_n)
  47.     if(!reset_n)
  48.         begin
  49.             st_cp <= 1'b0;
  50.             ds <= 1'b0;
  51.             sh_cp <= 1'd0;
  52.         end 
  53.     else 
  54.         begin
  55.             case(SHCP_EDGE_CNT)
  56.                 0: begin sh_cp <= 0; st_cp <= 1'd0;ds <= r_data[15];end
  57.                 1: begin sh_cp <= 1; st_cp <= 1'd0;end
  58.                 2: begin sh_cp <= 0; ds <= r_data[14];end
  59.                 3: begin sh_cp <= 1; end
  60.                 4: begin sh_cp <= 0; ds <= r_data[13];end    
  61.                 5: begin sh_cp <= 1; end
  62.                 6: begin sh_cp <= 0; ds <= r_data[12];end    
  63.                 7: begin sh_cp <= 1; end
  64.                 8: begin sh_cp <= 0; ds <= r_data[11];end    
  65.                 9: begin sh_cp <= 1; end
  66.                 10: begin sh_cp <= 0; ds <= r_data[10];end    
  67.                 11: begin sh_cp <= 1; end
  68.                 12: begin sh_cp <= 0; ds <= r_data[9];end    
  69.                 13: begin sh_cp <= 1; end
  70.                 14: begin sh_cp <= 0; ds <= r_data[8];end    
  71.                 15: begin sh_cp <= 1; end
  72.                 16: begin sh_cp <= 0; ds <= r_data[7];end    
  73.                 17: begin sh_cp <= 1; end
  74.                 18: begin sh_cp <= 0; ds <= r_data[6];end    
  75.                 19: begin sh_cp <= 1; end
  76.                 20: begin sh_cp <= 0; ds <= r_data[5];end    
  77.                 21: begin sh_cp <= 1; end
  78.                 22: begin sh_cp <= 0; ds <= r_data[4];end    
  79.                 23: begin sh_cp <= 1; end
  80.                 24: begin sh_cp <= 0; ds <= r_data[3];end    
  81.                 25: begin sh_cp <= 1; end
  82.                 26: begin sh_cp <= 0; ds <= r_data[2];end    
  83.                 27: begin sh_cp <= 1; end
  84.                 28: begin sh_cp <= 0; ds <= r_data[1];end            
  85.                 29: begin sh_cp <= 1; end
  86.                 30: begin sh_cp <= 0; ds <= r_data[0];end
  87.                 31: begin sh_cp <= 1; end
  88.                 32: st_cp <= 1'd1;
  89.                 default:        
  90.                     begin
  91.                         st_cp <= 1'b0;
  92.                         ds <= 1'b0;
  93.                         sh_cp <= 1'd0;
  94.                     end
  95.             endcase
  96.         end
  97.  
  98.         
  99.         
  100.         
  101. endmodule

key_adc_hex8.v

  1.  
  2. module key_adc_hex8(
  3.                  input clk , 
  4.                  input reset_n,
  5.                  input key,
  6.                  
  7.                  input [2:0]Addr,
  8.                  input ADC_DOUT,
  9.                  output  ADC_SCLK,
  10.                  output  ADC_CS_N,
  11.                  output  ADC_DIN,
  12.                  output  Conv_Done,
  13.                  
  14.                  output sh_cp,
  15.                  output st_cp,
  16.                  output ds
  17.                     );
  18.                     
  19.                     
  20.      wire key_flag , key_state ;               
  21.      key_one key_one_(
  22.                      . clk(clk) , 
  23.                      . reset_n(reset_n),
  24.                      . key(key),
  25.                      . key_flag(key_flag),
  26.                      . key_state(key_state)
  27.                      );     
  28.                      
  29.                                
  30.          reg  Conv_Go ;  
  31.          always@(posedge clk or negedge reset_n )
  32.          if(!reset_n ) 
  33.             Conv_Go <= 1'b0 ;
  34.          else if((key_flag)&&(key_state==1))
  35.             Conv_Go <= 1'b1 ;
  36.          else
  37.             Conv_Go <= 1'b0 ;
  38.         
  39.       wire [11:0]  Data;
  40.      adc128s102 adc_(
  41.                 . clk(clk),
  42.                 . reset_n(reset_n),
  43.                 
  44.                 . Conv_Go(Conv_Go),//使能信号
  45.                 . Addr(Addr),
  46.                 
  47.                 . ADC_DOUT(ADC_DOUT),
  48.                 . ADC_SCLK(ADC_SCLK),
  49.                 . ADC_CS_N(ADC_CS_N),
  50.                 . ADC_DIN(ADC_DIN),
  51.                 
  52.                 . Conv_Done(Conv_Done),
  53.                 . Data(Data)
  54.                 );   
  55.         
  56.     reg [31:0]disp_data;
  57.     wire [7:0] sel;//数码管位选（选择当前要显示的数码管）
  58.     wire [7:0] seg;//数码管段选（当前要显示的内容)  
  59.     always@(posedge clk or negedge reset_n )
  60.      if(!reset_n ) 
  61.         disp_data <= 0 ;
  62.      else 
  63.         disp_data <= 32'h0000_0000 + Data ;    
  64.                     
  65.      
  66.      hc595_driver hc595_driver(
  67.         .clk(clk),
  68.         .reset_n(reset_n),
  69.         .data({seg,sel}),  //将段选与位选信号拼接在一起
  70.         .s_en(1'b1),
  71.         .sh_cp(sh_cp),
  72.         .st_cp(st_cp),
  73.         .ds(ds)
  74.     );
  75.     
  76.     hex_8 hex8(
  77.         .clk(clk),
  78.         .reset_n(reset_n),
  79.         .disp_data(disp_data),
  80.         .sel(sel),
  81.         .seg(seg)
  82.     );
  83.      
  84.      
  85.                     
  86. endmodule

key_adc_hex8_tb.v

  1. `timescale 1ns / 1ns
  2.  
  3. module key_adc_hex8_tb(    );
  4.         
  5.         reg clk;
  6.         reg reset_n;
  7.         reg key ;
  8.         reg [2:0]Addr;
  9.         reg ADC_DOUT;
  10.         wire ADC_SCLK;
  11.         wire ADC_CS_N;
  12.         wire ADC_DIN;
  13.         wire Conv_Done;
  14.         wire sh_cp,st_cp, ds;
  15.         
  16.         
  17.      key_adc_hex8    k_hex8(
  18.                   clk , 
  19.                   reset_n,
  20.                   key,
  21.                  
  22.                 Addr,
  23.                   ADC_DOUT,
  24.                    ADC_SCLK,
  25.                    ADC_CS_N,
  26.                    ADC_DIN,
  27.                    Conv_Done,
  28.                  
  29.                   sh_cp,
  30.                   st_cp,
  31.                   ds
  32.                     );
  33.         
  34.      initial clk = 1;
  35.         always #10 clk = ~clk;
  36.         
  37.          initial 
  38.     begin
  39.         reset_n = 0;
  40.         Addr = 2;
  41.         key = 1 ;
  42.         #201;
  43.         reset_n = 1;
  44.         #200;
  45.         key_press(2);
  46.          
  47.         wait(!ADC_CS_N);
  48.         //16'h0A58
  49.         @(negedge ADC_SCLK);
  50.         ADC_DOUT = 0; //DB15 
  51.         @(negedge ADC_SCLK);
  52.         ADC_DOUT = 0; //DB14 
  53.         @(negedge ADC_SCLK);
  54.         ADC_DOUT = 0; //DB13        
  55.         @(negedge ADC_SCLK);
  56.         ADC_DOUT = 0; //DB12        
  57.         @(negedge ADC_SCLK);
  58.         ADC_DOUT = 1; //DB11          
  59.         @(negedge ADC_SCLK);
  60.         ADC_DOUT = 0; //DB10         
  61.         @(negedge ADC_SCLK);
  62.         ADC_DOUT = 1; //DB9         
  63.         @(negedge ADC_SCLK);
  64.         ADC_DOUT = 0; //DB8         
  65.         @(negedge ADC_SCLK);
  66.         ADC_DOUT = 0; //DB7         
  67.         @(negedge ADC_SCLK);
  68.         ADC_DOUT = 1; //DB6         
  69.         @(negedge ADC_SCLK);
  70.         ADC_DOUT = 0; //DB5         
  71.         @(negedge ADC_SCLK);
  72.         ADC_DOUT = 1; //DB4        
  73.         @(negedge ADC_SCLK);
  74.         ADC_DOUT = 1; //DB3         
  75.         @(negedge ADC_SCLK);
  76.         ADC_DOUT = 0; //DB2        
  77.         @(negedge ADC_SCLK);
  78.         ADC_DOUT = 0; //DB1         
  79.         @(negedge ADC_SCLK);
  80.         ADC_DOUT = 0; //DB0      
  81.         wait(ADC_CS_N);
  82.         #2000;   
  83.          #1000000;    
  84.         
  85.         Addr = 7;
  86.         #20;
  87.       key_press(2);     
  88.         wait(!ADC_CS_N);
  89.         //16'h0893
  90.         @(negedge ADC_SCLK);
  91.         ADC_DOUT = 0;
  92.         @(negedge ADC_SCLK);
  93.         ADC_DOUT = 0;
  94.         @(negedge ADC_SCLK);
  95.         ADC_DOUT = 0;        
  96.         @(negedge ADC_SCLK);
  97.         ADC_DOUT = 0;        
  98.         @(negedge ADC_SCLK);
  99.         ADC_DOUT = 1;          
  100.         @(negedge ADC_SCLK);
  101.         ADC_DOUT = 0;         
  102.         @(negedge ADC_SCLK);
  103.         ADC_DOUT = 0;         
  104.         @(negedge ADC_SCLK);
  105.         ADC_DOUT = 0;         
  106.         @(negedge ADC_SCLK);
  107.         ADC_DOUT = 1;         
  108.         @(negedge ADC_SCLK);
  109.         ADC_DOUT = 0;         
  110.         @(negedge ADC_SCLK);
  111.         ADC_DOUT = 0;         
  112.         @(negedge ADC_SCLK);
  113.         ADC_DOUT = 1;         
  114.         @(negedge ADC_SCLK);
  115.         ADC_DOUT = 0;         
  116.         @(negedge ADC_SCLK);
  117.         ADC_DOUT = 0;         
  118.         @(negedge ADC_SCLK);
  119.         ADC_DOUT = 1;         
  120.         @(negedge ADC_SCLK);
  121.         ADC_DOUT = 1;       
  122.         wait(ADC_CS_N);
  123.         #200;    
  124.         #1000000;
  125.  
  126.  
  127.  
  128.  
  129.  
  130.  
  131.         $stop;
  132.     end
  133. reg [13:0] rand;
  134.  task key_press;
  135.     input[3:0]seed;
  136.     begin
  137.         key =  1 ;
  138.         #100000;
  139.         repeat(10)
  140.             begin
  141.                 rand = {$random(seed)} % 10000;
  142.                 #rand;
  143.                 key=~key;
  144.             end
  145.         key = 0 ;
  146.         #100000;
  147.          key =  1 ;
  148.     end 
  149. endtask          
  150.  
  151. endmodule

.xdc

  1. set_property IOSTANDARD LVCMOS33 [get_ports clk]
  2. set_property IOSTANDARD LVCMOS33 [get_ports reset_n]
  3. set_property IOSTANDARD LVCMOS33 [get_ports st_cp]
  4. set_property IOSTANDARD LVCMOS33 [get_ports sh_cp]
  5. set_property IOSTANDARD LVCMOS33 [get_ports ds]
  6.  
  7. set_property PACKAGE_PIN U18 [get_ports clk]
  8. set_property PACKAGE_PIN D20 [get_ports ds]
  9. set_property PACKAGE_PIN E19 [get_ports sh_cp]
  10. set_property PACKAGE_PIN F17 [get_ports st_cp]
  11.  
  12. set_property IOSTANDARD LVCMOS33 [get_ports {Addr[2]}]
  13. set_property IOSTANDARD LVCMOS33 [get_ports {Addr[1]}]
  14. set_property IOSTANDARD LVCMOS33 [get_ports {Addr[0]}]
  15. set_property IOSTANDARD LVCMOS33 [get_ports ADC_CS_N]
  16. set_property IOSTANDARD LVCMOS33 [get_ports ADC_DIN]
  17. set_property IOSTANDARD LVCMOS33 [get_ports ADC_DOUT]
  18. set_property IOSTANDARD LVCMOS33 [get_ports ADC_SCLK]
  19. set_property IOSTANDARD LVCMOS33 [get_ports Conv_Done]
  20. set_property IOSTANDARD LVCMOS33 [get_ports key]
  21. set_property PACKAGE_PIN H18 [get_ports key]
  22. set_property PACKAGE_PIN H20 [get_ports reset_n]
  23. set_property PACKAGE_PIN K14 [get_ports {Addr[0]}]
  24. set_property PACKAGE_PIN L15 [get_ports {Addr[1]}]
  25. set_property PACKAGE_PIN G14 [get_ports {Addr[2]}]
  26. set_property PACKAGE_PIN M19 [get_ports ADC_DIN]
  27. set_property PACKAGE_PIN M20 [get_ports ADC_DOUT]
  28. set_property PACKAGE_PIN L19 [get_ports ADC_SCLK]
  29. set_property PACKAGE_PIN M18 [get_ports ADC_CS_N]
  30. set_property PACKAGE_PIN G17 [get_ports Conv_Done]

分析

测试代码符合预期

板级验证：

拨码开关选取地址

测量短路时，电压为0

测量小电池，电压比较准（手边没万用表，划划水啦~）

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