UD SOM系列兼容性_jfm9vu13p

作者：盐析白兔 | 2024-05-14 06:12:48

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jfm9vu13p

SOM全称为System-on-Modules，UD的SOM板既是FPGA或嵌入式系统的核心板，又可以独立使用。板子尺寸为74mm x 130mm，板对板连接器高度为10mm。当作为VPX、PXIe等3U载板时，单宽不超高。

SOM系列主要有SOM-404（基于JFM7VX690T或XC7VX690T FPGA）、SOM-403（基于JFM9VU13P或XC9VU13P FPGA）、SOM-402（基于JFMQL100T或ZYNQ 045T/100T）、SOM-403（基于JFM7K410T+FT-M6678N或XC7K325T/XC7K410T+FT-M6678N）系列。用户设计载板时，需要考虑系列的兼容性。

产品型号		UD SOM-404		UD SOM-403		UD SOM-405		UD SOM-402
电平	FMC+0	JFM7VX690T80		JFM9VU13PB2104		JFM7K410T+FT-M6678N		JFMQL100T900
	FMC_DP0	BANK111_GTH[0]	PCIe0[7]	BANK225_GTY[3]	PCIe[7]	BANK115_GTX[0]	DSP_SRIO[3]	BANK111_GTX[0]	PL_PCIe[7]
	FMC_DP1	BANK111_GTH[1]	PCIe0[6]	BANK225_GTY[2]	PCIe[6]	BANK115_GTX[1]	DSP_SRIO[2]	BANK111_GTX[1]	PL_PCIe[6]
	FMC_DP2	BANK111_GTH[2]	PCIe0[5]	BANK225_GTY[1]	PCIe[5]	BANK115_GTX[2]	DSP_SRIO[1]	BANK111_GTX[2]	PL_PCIe[5]
	FMC_DP3	BANK111_GTH[3]	PCIe0[4]	BANK225_GTY[0]	PCIe[4]	BANK115_GTX[3]	DSP_SRIO[0]	BANK111_GTX[3]	PL_PCIe[4]
	FMC_DP4	BANK112_GTH[0]	PCIe0[3]	BANK224_GTY[3]	PCIe[3]	BANK116_GTX[0]	FPGA_PCIe[3]	BANK112_GTX[0]	PL_PCIe[3]
	FMC_DP5	BANK112_GTH[1]	PCIe0[2]	BANK224_GTY[2]	PCIe[2]	BANK116_GTX[1]	FPGA_PCIe[2]	BANK112_GTX[1]	PL_PCIe[2]
	FMC_DP6	BANK112_GTH[2]	PCIe0[1]	BANK224_GTY[1]	PCIe[1]	BANK116_GTX[2]	FPGA_PCIe[1]	BANK112_GTX[2]	PL_PCIe[1]
	FMC_DP7	BANK112_GTH[3]	PCIe0[0]	BANK224_GTY[0]	PCIe[0]	BANK116_GTX[3]	FPGA_PCIe[0]	BANK112_GTX[3]	PL_PCIe[0]
	CLK2_BIDR	BANK112_REF1	PCIe0_CLK_C2M	BANK224_REF1	PCIe0_CLK_C2M	BANK115_REF1	FPGA_PCIe_CLK_C2M		PL_PCIe_CLK_C2M
LVDS1.8V	LA33[P]		PCIe0_RST_N		PCIe0_RST_N		FPGA_PCIe_RST_N		PL_PCIe_RST_N
LVDS1.8V	LA33[N]		PCIe0_WAKE_N		PCIe0_WAKE_N		FPGA_PCIe_WAKE_N		PL_PCIe_WAKE_N
	CLK0_M2C		PCIe0_CLK_M2C		PCIe0_CLK_M2C		FPGA_PCIe_CLK_M2C		PL_PCIe_CLK_M2C
	FMC_DP8	BANK114_GTH[0]	PCIe1[7]	BANK227_GTY[3]	PCIe[15]
	FMC_DP9	BANK114_GTH[1]	PCIe1[6]	BANK227_GTY[2]	PCIe[14]
	FMC_DP10	BANK114_GTH[2]	PCIe1[5]	BANK227_GTY[1]	PCIe[13]
	FMC_DP11	BANK114_GTH[3]	PCIe1[4]	BANK227_GTY[0]	PCIe[12]
	FMC_DP12	BANK115_GTH[0]	PCIe1[3]	BANK226_GTY[3]	PCIe[11]		DSP_PCIe[3]
	FMC_DP13	BANK115_GTH[1]	PCIe1[2]	BANK226_GTY[2]	PCIe[10]		DSP _PCIe[2]
	FMC_DP14	BANK115_GTH[2]	PCIe1[1]	BANK226_GTY[1]	PCIe[9]		DSP _PCIe[1]
	FMC_DP15	BANK115_GTH[3]	PCIe1[0]	BANK226_GTY[0]	PCIe[8]		DSP _PCIe[0]
	CLK3_BIDR	BANK115_REF1	PCIe1_CLK_C2M	BANK226_REF1	PCIe1_CLK_C2M		DSP_PCIe_CLK_C2M
LVDS1.8V	LA32[P]		PCIe1_RST_N		PCIe1_RST_N		DSP _PCIe_RST_N
LVDS1.8V	LA32[N]		PCIe1_WAKE_N		PCIe1_WAKE_N		DSP _PCIe_WAKE_N
	CLK1_M2C		PCIe1_CLK_M2C		PCIe1_CLK_M2C		DSP_PCIe_CLK_M2C
TTL3.3V			FPGA_JTAG_3.3V_M2C		FPGA_JTAG_3.3V_M2C		FPGA_JTAG_3.3V_M2C		FPGA_JTAG_3.3V_M2C
TTL3.3V			FPGA_TCK_C2M		FPGA_TCK_C2M		FPGA_TCK_C2M		FPGA_TCK_C2M
TTL3.3V			FPGA_TDO_M2C		FPGA_TDO_M2C		FPGA_TDO_M2C		FPGA_TDO_M2C
TTL3.3V			FPGA_TDI_C2M		FPGA_TDI_C2M		FPGA_TDI_C2M		FPGA_TDI_C2M
TTL3.3V			FPGA_TMS_C2M		FPGA_TMS_C2M		FPGA_TMS_C2M		FPGA_TMS_C2M
TTL1.8V			UPDATA_M1		UPDATA_M1
TTL1.8V			UPDATA_M2		UPDATA_M2
TTL1.8V			UPDATA_PROG_B		UPDATA_PROG_B
TTL1.8V			UPDATA_DONE		UPDATA_DONE
TTL1.8V			UPDATA_INIT_N		UPDATA_INIT_N
TTL1.8V			UPDATA_DIN		UPDATA_DIN
TTL1.8V			UPDATA_CCLK		UPDATA_CCLK
TTL3.3V							DSP _TMS_C2M
TTL3.3V							DSP_TRST_N_C2M
TTL3.3V							DSP_TDI_C2M
TTL3.3V							DSP_JTAG_3.3V_M2C
TTL3.3V							DSP _TDO_M2C
TTL3.3V							DSP _TCK_C2M
TTL3.3V							DSP_UART_TX		PS_UART1_TX
TTL3.3V							DSP_UART_RX		PS_UART1_RX
TTL3.3V							FPGA_UART_TX		PS_UART2_TX
TTL3.3V							FPGA_UART_RX		PS_UART2_RX
							DSP_ETH_MDI0_P/N		PS_ETH1_MDI0_P/N
							DSP_ETH_MDI1_P/N		PS_ETH1_MDI1_P/N
							DSP_ETH_MDI2_P/N		PS_ETH1_MDI2_P/N
							DSP_ETH_MDI3_P/N		PS_ETH1_MDI3_P/N
							DSP_ETH_TRANS_TCT_M2C		PS _ETH1_TRANS_TCT_M2C
							DSP_ETH_LED_VCC_M2C		PS_ETH1_LED_VCC_M2C
							DSP_ETH_LED_LINK		PS_ETH1_LED_LINK
							DSP_ETH_LED_ACT		PS_ETH1_LED_ACT
TTL3.3V							DSP_1553_CLK
							DSP_1553_TXA_P/N		PS_ETH2_MDI0_P/N
							DSP_1553_TXB_P/N		PS_ETH2_MDI1_P/N
							DSP_1553_RXA_P/N		PS_ETH2_MDI2_P/N
							DSP_1553_RXB_P/N		PS_ETH2_MDI3_P/N
TTL3.3V							DSP_1553_RXA_EN		PS _ETH2_TRANS_TCT_M2C
TTL3.3V							DSP_1553_RXB_EN		PS_ETH2_LED_VCC_M2C
TTL3.3V							DSP_1553_TXA_BUSY		PS_ETH2_LED_LINK
TTL3.3V							DSP_1553_TXB_ BUSY		PS_ETH2_LED_ACT
TTL3.3V									PS_CAN0_TXD
TTL3.3V									PS_CAN0_RXD
TTL3.3V									PS_CAN1_TXD
TTL3.3V									PS_CAN1_RXD
									PS_USB0_5V_EN
									PS_USB0_D+
									PS_USB0_D-
									PS_USB0_ID
									PS_USB1_5V_EN
									PS_USB1_D+
									PS_USB1_D-
									PS_USB1_ID
12V输入							+12V

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