xilinx mutiboot那些坑

Spartan6 multiboot原理

基本原理，不多说，百度可以找到，基本配置也不说可以参考Spartan6 Mutiboot实现方法记录，我要说的是如何真从multi imge跳转会golden image，其实方法很简单，只是很少有人分享出来。今天我来说一下，实现这个功能的原因是当multi image出错时为了保证设备能正常运行，需要跳转会golden image不影响设备工作，具体配置很简单，在golden image的工程文件增加icap机制，增加文件icmp_ctrl.v

module ICMP_CTRL(
	input					icap_clk,
	input					start,
	input	[23:0]			MultiBoot_addr,
	input	[23:0]			Fallback_addr
    );
 
	localparam				SPIx1 = 8'h03;//也可以是03,具体参考flash数据手册，查看相关操作码
	
	reg						CE=1;
	reg						WRITE=0;
	reg	[15:0]				I=0;
	reg	[16:0]				cnt=16'D32;
	
	always @ (negedge icap_clk)
	begin
		if(start)
			cnt <= 16'd0;
		else
			if(cnt < 16'd32)
				cnt <= cnt + 1'b1;
			else
				cnt <= 16'd32;	
	end
	
	always @ (negedge icap_clk)
	begin
		case(cnt)
			16'd1	:	begin
							CE <= 1'b1;
							I <= 16'd0;
							WRITE <= 0;
						end
			16'd2	:	begin
							CE <= 1'b0;
							I <= 16'hFFFF;
							WRITE <= 0;
						end
			16'd3	:	begin
							CE <= 1'b0;
							I <= 16'hFFFF;
							WRITE <= 0;
						end
			16'd4	:	begin
							CE <= 1'b0;
							I <= 16'hAA99;
							WRITE <= 0;
						end
			16'd5	:	begin
							CE <= 1'b0;
							I <= 16'h5566;
							WRITE <= 0;
						end
			16'd6	:	begin
							CE <= 1'b0;
							I <= 16'h3261;
							WRITE <= 0;
						end
			16'd7	:	begin
							CE <= 1'b0;
							I <= MultiBoot_addr[15:0];
							WRITE <= 0;
						end
			16'd8	:	begin
							CE <= 1'b0;
							I <= 16'h3281;
							WRITE <= 0;
						end
			16'd9	:	begin
							CE <= 1'b0;
							I <= {SPIx1,MultiBoot_addr[23:16]};
							WRITE <= 0;
						end
			16'd10	:	begin
							CE <= 1'b0;
							I <= 16'h32A1;
							WRITE <= 0;
						end
			16'd11	:	begin
							CE <= 1'b0;
							I <= Fallback_addr[15:0];
							WRITE <= 0;
						end
			16'd12	:	begin
							CE <= 1'b0;
							I <= 16'h32C1;
							WRITE <= 0;
						end
			16'd13	:	begin
							CE <= 1'b0;
							I <= {SPIx1,Fallback_addr[23:16]};
							WRITE <= 0;
						end
			16'd14	:	begin
							CE <= 1'b0;
							I <= 16'H30A1;
							WRITE <= 0;
						end
			16'd15	:	begin
							CE <= 1'b0;
							I <= 16'H000E;
							WRITE <= 0;
						end
			16'd16	:	begin
							CE <= 1'b0;
							I <= 16'H2000;
							WRITE <= 0;
						end
			16'd17	:	begin
							CE <= 1'b0;
							I <= 16'H2000;
							WRITE <= 0;
						end
			16'd18	:	begin
							CE <= 1'b0;
							I <= 16'H2000;
							WRITE <= 0;
						end
			16'd19	:	begin
							CE <= 1'b0;
							I <= 16'H2000;
							WRITE <= 0;
						end
			16'd20	:	begin
							CE <= 1'b1;
							I <= 16'H2000;
							WRITE <= 0;
						end
			default	:	begin
							CE <= 1'b1;
							I <= 16'H0000;
							WRITE <= 0;			
						end		
		endcase
	end
	
	wire	[15:0]			icap_i;
	
	assign 					icap_i[15] = I[ 8];
	assign 					icap_i[14] = I[ 9];
	assign 					icap_i[13] = I[10];
	assign 					icap_i[12] = I[11];
	assign 					icap_i[11] = I[12];
	assign 					icap_i[10] = I[13];
	assign 					icap_i[ 9] = I[14];
	assign 					icap_i[ 8] = I[15];
											
	assign 					icap_i[ 7] = I[ 0];
	assign 					icap_i[ 6] = I[ 1];
	assign 					icap_i[ 5] = I[ 2];
	assign 					icap_i[ 4] = I[ 3];
	assign 					icap_i[ 3] = I[ 4];
	assign 					icap_i[ 2] = I[ 5];
	assign 					icap_i[ 1] = I[ 6];
	assign 					icap_i[ 0] = I[ 7];
	
	ICAP_SPARTAN6 #(
	.DEVICE_ID(32'h2400e093), // Specifies the pre-programmed Device ID value
	.SIM_CFG_FILE_NAME("NONE") // Specifies the Raw Bitstream (RBT) file to be parsed by         the simulation
	)
	ICAP_SPARTAN6_inst(
		.BUSY(), // 1-bit output: Busy/Ready output
		.O(), // 16-bit output: Configuartion data output bus
		.CE(CE), // 1-bit input: Active-Low ICAP Enable input
		.CLK(icap_clk), // 1-bit input: Clock input
		.I(icap_i), // 16-bit input: Configuration data input bus
		.WRITE(1'b0) // 1-bit input: Read/Write control input
	);
 
endmodule
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顶层文件例化

 ICMP_CTRL ICMP_CTRL(
	.icap_clk(sysclk),
	.start(~rssst_n),
	.MultiBoot_addr(24'h258000),//multi image起始地址
	.Fallback_addr(24'h000044)  //golden image起始地址
    );
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这样生成bin文件后，就可以试下固件跳转