verilog 学习笔记 —— 时序逻辑 Sequential Logics (Latches and Flip-Flops 锁存器和触发器)_门控制d锁存器的verilog测试代码

1. D flip-flop D触发器

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//
 
    // Use a clocked always block
    //   copy d to q at every positive edge of clk
    //   Clocked always blocks should use non-blocking assignments
    always@(posedge clk)   //固定格式
        begin
             q <= d ;   // 非阻塞赋值，顺序执行
        end
 
endmodule

2. D flip-flop  D触发器

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    // Because q is a vector, this creates multiple DFFs.
    always@(posedge clk)
        begin
            q <= d ;
        end
 
endmodule

3. DFF with reset  带复位的D触发器 

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk)
        begin
            if(reset)
                q <= 8'b0;
            else
                q <= d ;
        end
 
endmodule

4. 带复位值的D触发器

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always@(negedge clk)
        begin
            if(reset)
                q <= 8'H0x34 ;
            else
                q<=d;
        end
 
endmodule

5. DFF with asynchronous reset 带异步复位功能的 D触发器

module top_module(
	input clk,
	input [7:0] d,
	input areset,
	output reg [7:0] q);
	
	// The only difference in code compared to synchronous reset is in the sensitivity list.
	always @(posedge clk, posedge areset)
		if (areset)
			q <= 0;
		else
			q <= d;
 
 
	// In Verilog, the sensitivity list looks strange. The FF's reset is sensitive to the
	// *level* of areset, so why does using "posedge areset" work?
	// To see why it works, consider the truth table for all events that change the input 
	// signals, assuming clk and areset do not switch at precisely the same time:
	
	//  clk		areset		output
	//   x		 0->1		q <= 0; (because areset = 1)   上升沿触发  复位
	//   x		 1->0		no change (always block not triggered)
	//  0->1	   0		q <= d; (not resetting)        上升沿触发  复位
	//  0->1	   1		q <= 0; (still resetting, q was 0 before too)    复位
	//  1->0	   x		no change (always block not triggered)
	
endmodule

6. DFF with byte enable   带位启动的触发器

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always@(posedge clk)
        begin
            if(!resetn)
                q <= 16'b0;
            else
                begin
                    if(byteena[0])
                        q[7:0] <= d[7:0];
                    if(byteena[1])   
                        q[15:8] <=d[15:8];
                end
        end
 
 
endmodule

7. D Latch  D锁存器

module top_module (
    input d, 
    input ena,
    output q);
    always@(*)
        begin
            if(ena)
                q<=d;
        end
 
endmodule

8. DFF

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset  异步复位
    output q);
    always@(posedge clk, posedge ar)  //异步复位，always语句条件需要注明
        begin
            if(ar)
                q<=1'b0;
            else
                q<=d;
        end
 
endmodule

 9. DFF

 

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset  同步复位
    output q);
    always@(posedge clk)
        begin
            if(r)
                q<=0;
            else
                q<=d;
        end
 
endmodule

10. DFF+gate

 

module top_module (
    input clk,
    input in, 
    output out);
    always@(posedge clk)
        begin
            out<=in^out;
        end
 
endmodule

11. Mux and DFF

 

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    wire D;
    assign D=L?r_in:q_in;   //多路复用器
    always@(posedge clk)    //触发器
        begin
            Q<=D;
        end
 
endmodule

12. DFFs and gates

 

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    wire W,D;             //多路复用器
    assign W=E?w:Q;
    assign D=L?R:W;
    always@(posedge clk)  //触发器
        begin
            Q<=D;
        end
 
endmodule

13.  DFFs and gates

 

module top_module (
    input clk,
    input x,
    output z
); 
    wire Q1,Q2,Q3;
    wire D1,D2,D3;
    assign D1=x^Q1;
    assign D2=x&~Q2;
    assign D3=x|~Q3;
    assign z=~(Q1|Q2|Q3);
    always@(posedge clk)
        begin
            Q1<=D1;
            Q2<=D2;
            Q3<=D3;
        end
    
 
endmodule

14. Create circuit from turth table 

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    wire D;
    assign D=j&~Q | ~k&Q;
    always@(posedge clk)
        begin
            Q<=D;
        end
endmodule

15. Detect and edge  输入的单边沿检测

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] mid;
    always@(posedge clk)
        begin
            mid<=in;  //把上一周期的in值赋给mid
            pedge<=~mid&in;  //上一周期in为0，这一周期in为1,pedge才会有值
        end
 
endmodule

16. Detect both edges  输入的双边沿检测

 

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0]mid;
 
    always@(posedge clk)
        begin 
            mid<=in;        //把上一周期的In值赋给mid
            anyedge <= ~mid&in | mid&~in ;  //上一周期0现在1  或者  上一周期1现在0  
        end
        
 
endmodule

 17. Edge capture register  边沿捕获寄存器

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0] mid;
    always@(posedge clk)
        begin
            mid <= in;
            if(reset)
                out <= 4'h0;   //复位前保持高电平，复位后变为低电平
            else
                out <= mid&~in | out ;   //   |out  表示    会保持高电平，直到收到复位信号
        end
endmodule

 18. Dual-edge triggered flip-flop  时钟的双边沿捕获

 

module top_module (
    input clk,
    input d,
    output q
);
    reg q0,q1;
    always@(posedge clk)
        begin 
            q0 <= d;    //q0为上升沿触发的输出
        end
    always@(negedge clk)
        begin
            q1 <= d;    //q1为下降沿触发的输出
        end
    assign q = clk?q0:q1;  //根据时钟clk决定，最终使用哪一段 输出
 
endmodule

module top_module(
	input clk,
	input d,
	output q);
	
	reg p, n;
	
	// A positive-edge triggered flip-flop
    always @(posedge clk)
        p <= d ^ n;
        
    // A negative-edge triggered flip-flop
    always @(negedge clk)
        n <= d ^ p;
    
    // Why does this work? 
    // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
    // After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d.
    // At each (positive or negative) clock edge, p and n FFs alternately
    // load a value that will cancel out the other and cause the new value of d to remain.
    assign q = p ^ n;
    
    
	// Can't synthesize this.
	/*always @(posedge clk, negedge clk) begin
		q <= d;
	end*/
    
    
endmodule