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TQZC706开发板教程:在ZC706上运行ADRV9371(vivado2018.3)

TQZC706开发板教程:在ZC706上运行ADRV9371(vivado2018.3)

首先需要在github上下载两个文件,本例程用到的文件以及最终文件,我都会放在网盘里面,地址在本文的末尾,需要自行提取

在github上搜索hdl选择第一个-->选择版本-->我所使用的vivado是2018.3版本,所以这里我下载的是hdl_2019_r1-->在附录中下载资源-->下载对应版本的No-Os

把下载好的资源复制到虚拟机里解压缩,右键打开命令行

设置环境变量-->进入项目目录-->编译-->打开vivado

  1. source /tools/Xilinx/Vivado/2018.3/settings64.sh
  2. cd hdl-2019_r1/projects/adrv9371x/zc706
  3. make
  4. vivado

打开工程-->选择工程-->确定

不需要修改直接编译

导出硬件设计,后续弹出的提示都选择确认

打开SDK,后续弹出的提示都选择确认

新建项目

项目名称设置为fsbl-->next-->选择FSBL-->完成。注意SDK不要关闭,后续需要用其生成BOOT.bin

回到最开始的目录,右键再次打开一个命令行窗口

设置环境变量-->进入工程目录-->复制硬件设计文件-->编译工程,等待编译成功

  1. source /tools/Xilinx/Vivado/2018.3/settings64.sh
  2. cd no-OS-2019_R1/projects/ad9371/
  3. cp ../../../hdl-2019_r1/projects/adrv9371x/zc706/adrv9371x_zc706.sdk/system_top.hdf .
  4. make

回到最开始的目录,右键再次打开一个命令行窗口

创建file文件夹-->进入文件夹-->复制fsbl文件-->复制bit文件-->复制elf文件

  1. mkdir file
  2. cd file
  3. cp ../hdl-2019_r1/projects/adrv9371x/zc706/adrv9371x_zc706.sdk/fsbl/Debug/fsbl.elf .
  4. cp ../hdl-2019_r1/projects/adrv9371x/zc706/adrv9371x_zc706.runs/impl_1/system_top.bit .
  5. cp ../no-OS-2019_R1/projects/ad9371/build/release.elf .

回到SDK,生成BOOT文件

选择file文件夹-->按照顺序添加file中的文件(顺序为:fsbl-->bit-->elf)-->生成BOOT文件

打开file文件夹复制BOOT.bin文件到SD卡中,插入开发板,接好电源,串口线,安装好ADRV9371模块,启动模式设置为SD卡启动

打开串口助手软件,开启电源等待串口打印信息,最后输出Done表示成功

  1. Please wait...
  2. WARNING: AD9528_initialize() issues. Possible cause: REF_CLK not connected.
  3. rx_clkgen: MMCM-PLL locked (122880000 Hz)
  4. tx_clkgen: MMCM-PLL locked (122880000 Hz)
  5. rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
  6. MCS successful
  7. CLKPLL locked
  8. AD9371 ARM version 5.2.2
  9. PLLs locked
  10. Calibrations completed successfully
  11. tx_adxcvr: OK (4915200 kHz)
  12. rx_adxcvr: OK (4915200 kHz)
  13. rx_os_adxcvr: OK (4915200 kHz)
  14. rx_jesd status:
  15. Link is enabled
  16. Measured Link Clock: 122.865 MHz
  17. Reported Link Clock: 122.880 MHz
  18. Lane rate: 4915.200 MHz
  19. Lane rate / 40: 122.880 MHz
  20. Link status: DATA
  21. SYSREF captured: Yes
  22. SYSREF alignment error: No
  23. rx_jesd lane 0 status:
  24. Errors: 0
  25. CGS state: DATA
  26. Initial Frame Synchronization: Yes
  27. Lane Latency: 1 Multi-frames and 73 Octets
  28. Initial Lane Alignment Sequence: Yes
  29. DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
  30. K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
  31. FCHK: 0x47, CF: 0
  32. ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
  33. FC: 4915200 kHz
  34. rx_jesd lane 1 status:
  35. Errors: 1
  36. CGS state: DATA
  37. Initial Frame Synchronization: Yes
  38. Lane Latency: 1 Multi-frames and 74 Octets
  39. Initial Lane Alignment Sequence: Yes
  40. DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
  41. K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
  42. FCHK: 0x48, CF: 0
  43. ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
  44. FC: 4915200 kHz
  45. tx_jesd status:
  46. Link is enabled
  47. Measured Link Clock: 122.865 MHz
  48. Reported Link Clock: 122.880 MHz
  49. Lane rate: 4915.200 MHz
  50. Lane rate / 40: 122.880 MHz
  51. SYNC~: deasserted
  52. Link status: DATA
  53. SYSREF captured: Yes
  54. SYSREF alignment error: No
  55. rx_os_jesd status:
  56. Link is enabled
  57. Measured Link Clock: 122.864 MHz
  58. Reported Link Clock: 122.880 MHz
  59. Lane rate: 4915.200 MHz
  60. Lane rate / 40: 122.880 MHz
  61. Link status: DATA
  62. SYSREF captured: Yes
  63. SYSREF alignment error: No
  64. rx_os_jesd lane 0 status:
  65. Errors: 0
  66. CGS state: DATA
  67. Initial Frame Synchronization: Yes
  68. Lane Latency: 2 Multi-frames and 8 Octets
  69. Initial Lane Alignment Sequence: Yes
  70. DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
  71. K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
  72. FCHK: 0x43, CF: 0
  73. ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
  74. FC: 4915200 kHz
  75. rx_os_jesd lane 1 status:
  76. Errors: 0
  77. CGS state: DATA
  78. Initial Frame Synchronization: Yes
  79. Lane Latency: 2 Multi-frames and 6 Octets
  80. Initial Lane Alignment Sequence: Yes
  81. DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
  82. K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
  83. FCHK: 0x44, CF: 0
  84. ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
  85. FC: 4915200 kHz
  86. tx_dac: Successfully initialized (245730590 Hz)
  87. rx_adc: Successfully initialized (122865295 Hz)
  88. rx_obs_adc: Successfully initialized (245730590 Hz)
  89. Done

资源分享

整个项目最终文件与BOOT.bin

  1. 项目及BOOT.bin
  2. 链接:https://pan.baidu.com/s/1oxcjD2flhFfdV8PWVnOh_w
  3. 提取码:g31r
  4. 虚拟机镜像,内置vivado2018.3版本
  5. 链接:https://pan.baidu.com/s/13LNnIGnK-PFoAzuVh-1g-g
  6. 提取码:v06p

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