【XILINX】记录ISE/Vivado使用过程中遇到的一些warning及解决方案_module 'bufg' is not defined.

前言

        XILINX/AMD是大家常用的FPGA，但是在使用其开发工具ISE/Vivado时免不了会遇到很多warning，(大家是不是发现程序越大warning越多？)，并且还有很多warning根据消除不了，看着特心烦？

        我这里汇总一些我遇到的和记录的，给大家参考，祝大家都是0warning选手。

---

列表

warning：HDLCompiler:1499 - "*\RAM_16b_1k.v" Line 39: Empty module remains a black box.

在《Xilinx ISE 5.x 使用详解》中翻到如下内容：P71 

    书上有云： 

    “IP核在综合时一般被认为是黑盒子(Black Box)，综合器不对黑盒子做任何编译。将IP核加入工程有两种方法，一为在工程中新建Coregen IP类型资源，另一种是针对第三方综合工具而言，同时避免了在新工程中需要重新加入IP核资源的麻烦。也就是将IP核声明成黑盒子，具体操作时可以利用IP核生成时生成的仿真文件和IP核实例化文件(.veo,.vho)，将仿真文件中的IP核的相关部分原封不动地拷贝到顶层文件中去，声明IP核模块，然后将实例化文件内容粘贴到模块的实例化部分。 

    然面，使用Synplify Pro等综合工具综合IP核等Xilinx硬件原语时，需要调用相应Xilinx器件的硬件原语声明文件。位于Synpliy\lib\Xilinx”子目录中的virtex.v/vhd,virtexe.v/vhd,virtex2.v/vhd,virtex2p.v/vhd等文件就是硬件原语声明文件。调用时用"include"命令。 

（转帖）Xilinx CORE Generator心得 - cdy200824的日志 - 电子工程世界-论坛

在生成核开头的注释中加上如下注释

//synthesis attribute box_type "black_box" 

---

warning： HDLCompiler:413 - "*\NUC_RAM_INT.v" Line 145: Result of 10-bit expression is truncated to fit in 9-bit target.

计数器的累加值前加上

  cnt 1'b1;

---

"WARNING:Route:455 - CLK Net:trn_clk_OBUF may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template."

Solution

This message informs the user that some loads on the clock net are not clock pins. Therefore, the clock template that is normally used to connect clock pins will not be used to connect the loads. A different routing that involves local routing will be used, potentially inducing some skew on the clock net.

Opening your design in FPGA EDITOR will allow you to see what loads are connected to the clock net, and the cause of the warnings. The amount of skew on the net will be reported in the Place and Route report. If the loads on the net shown in FPGA Editor are in accord with your design, the skew reported in the PAR report is not critical for the design, and the timing constraint requirement on that net is met, then this warning can be safely ignored.

实例原因：在代码中用到这样的语句时（ aa’event and aa=’1’）， aa 不是时钟信号，最多只是时钟信号产生的一类周期信号， aa 被作为了另一个 进程或模块的类似周期信号的作用。（我是在行场信号发生器中 出现的这样的问题，用产生的行同步信号（行同步信号是由全局时钟信号驱动产生的）再去驱动产生场同步信号，产生的场同步信号相对与输入的全局时钟，有一定 的倾斜）

---

"WARNING:Xst:647 - Input is never used."or"WARNING:Xst:648 - Output is never used."Solution This particular port has been declared in your HDL description, but does not drive or is not driven by any internal logic. Unused input ports will remain in the design, but they will be completely unconnected. If the port is not intended to be used, this message can be safely ignored. To avoid this message, remove any loadless or sourceless elements from your HDL description. Output ports will remain in the final netlist and will be driven by a logic 0. To avoid the message and to save the port resource, remove the unused output port from your HDL description.

实例原因：一般输入端口不要预留，即使不使用，在代码中定义的输入端口就一定要有输入的；而输出端口不用到的可以用 OPEN 封上，最常见的是在利用 DLL 和 DCM 时，CLK90，CLK180，CLK270 等一般不用，在端口连接的时候都用 OPEN 封上。

---

Place:866 - Not enough valid sites to place the following IOBs:

IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR = BIDIR, DRIVE_STR = 12IO

This may be due to either an insufficient number of sites available on the device, too many prohibited sites,or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites.

This situation could possibly be resolved by one (or all) of the following actions:

a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints.

b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible.

c) If applicable, decreasing the number of user prohibited sites or using a larger device.

Pack:1654 - The timing-driven placement phase encountered an error.

原因：

Pack:1654 - The timing-driven placement phase encountered an error.

这个错位是由上一个错位866引起的。

866是因为顶层文件中输出信号名mcb1_rzq，但是ddr_mig中rzq的输出信号写的是rzq，这就导致rzq的输出连不上。

---

Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

Xst:1898 - Due to constant pushing, FF/Latch is unconnected in block .

解决方案：(*KEEP = "TRUE" *)reg [23:0] data_white_ori;

这些寄存器可以设置保留不被优化。

---

Xst:2677 - Node of sequential type is unconnected in block .

解决办法：That warning is caused by lot of things.....

One main reason is if your outputs are not connected..ie if you are not reading the module outputs the ise optimisation step removes all signal inside your block and fire a 2677 warning...

check the module outputs。

方法1：把定义多的，用不到的寄存器位宽改成合适大小。

方法2：(*KEEP = "TRUE" *)reg [15:0] ram_rd_data_reg=16'b0; 定义初值，并保持不被优化 有些添加后会出现其他类型的警告

---

Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

解决：(*KEEP = "TRUE" *)reg [ 7: 0] register_addr=8'b0;给初始值

---

HDLCompiler:634 - "*\rtl\ddr2_mig_6p.v" Line 365: Net does not have a driver.

线网没有驱动，那就给加个初值吧。

wire c3_p3_rd_clk=1'b0;

---

Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value GND.

信号被用到，但是没有赋初值，所以默认接到GND

加初值，解决问题 assign rd_franum = 9'd0;

---

HDLCompiler:189 - "*\poc_framavg.v" Line 298: Size mismatch in connection of port . Formal port size is 9-bit while actual signal size is 16-bit.

给输入接口的位宽不对，addra定义为9bit，给了10bit，改变输入数据的位宽为9bit。

---

ERROR:HDLParsers:3562 - pepExtractor.prj line 1 Expecting 'vhd ' or 'verilog' keyword, found 'work'。 SolutionThis occurs when there are spaces embedded in the project location.

A bad example for project location would be:C:/Documents and Settings/User/example.ise.

A good example fpr project location would be:C:/ISE_tests/example.ise.

实例原因：在 ISE9.1 的版本里，在行为仿真和使用约束编辑器的时候会遇到，主要原因是工程的路径名里有空格一类的不被要求的非英文字符。

---

"ERROR:Xst:2587 Port of instance has different

type in definition " .

Solution

Compare the component declaration and instantiation to the submodule that is instantiated. When this error occurs, the declaration matches the instantiation, but does not match the port declarations of the submodule.Change either the port declarations in the declaration/instantiation pair or the submodule port declarations so that they match. This error is specific to the types of ports in the submodule.

实例原因：一般是子模块宣称和子模块的实体定义中端口的宽度和类型(in, out, inout,buffer)不匹配造成的。

---

XST can generate very large log files for certain designs. In some cases, the generation of these log files can even cause an increase in runtime. How can I eliminate or hide certain frequently generated messages?

Solution

For users of XST via Project Navigator Starting in ISE 7.1i, Project Navigator has the capability to do message filtering for all Xilinx tools. Please refer to the Project Navigator help on how to use this method.

For users of XST via command line You can hide specific messages generated by XST at the HDL or Low-Level Synthesis steps in specific situations by using the XIL_XST_HIDEMESSAGES

environment variable. This environment variable can have one of the following values:

-- none: maximum verbosity. All messages are printed out. This is the default.

-- hdl_level: reduce verbosity during VHDL/Verilog Analysis and HDL Basic and Advanced Synthesis.

-- low_level: reduce verbosity during Low-level Synthesis

-- hdl_and_low_levels: reduce verbosity at all stages

The following messages are hidden when hdl_level or hdl_and_low_levels values are specified for the XIL_XST_HIDEMESSAGES environment variable:

WARNING:HDLCompilers:38 - design.v line xx Macro 'my_macro' redefined

NOTE: This message is issued by the Verilog compiler only.

WARNING:Xst:916 - design.vhd line xx: Delay is ignored for synthesis.

WARNING:Xst:766 - design.vhd line xx: Generating a Black Box for component comp.

Instantiating component comp from Library lib.

Set user-defined property "LOC = X1Y1" for instance inst in unit block.

Set user-defined property "RLOC = X1Y1" for instance inst in unit block.

Set user-defined property "INIT = 1" for instance inst in unit block.

Register reg1 equivalent to reg2 has been removed. The following messages are hidden when low_level or hdl_and_low_levels values are specified for the XIL_XST_HIDEMESSAGES environment variable:

WARNING:Xst:382 - Register reg1 is equivalent to reg2. Register reg1 equivalent to reg2 has been removed.

WARNING:Xst:1710 - FF/Latch reg (without init value) is constant in block block.

WARNING:Xst 1293 - FF/Latch reg is constant in block block.

WARNING:Xst:1291 - FF/Latch reg is unconnected in block block.

WARNING:Xst:1426 - The value init of the FF/Latch reg hinders the constant

cleaning in the block block. You could achieve better results by setting this init to value.

实例原因：在综合时，有很多的综合警告是可以忽略的，以上大致的罗列几项。

---

"WARNING:Xst:737 - Found n-bit latch for signal ." The listing for "n" is the width of the latch.If latch inference is intended, you can safely ignore this message.However, some inefficient coding styles can lead to accidental latch inference. You should analyze your code to see if this result is intended. The examples below illustrate how you can avoid latch inference.

实例原因：一般出现这样的问题都是代码出现了锁存器，因避免这样的代码写法，电路会不稳定，因利用触发器去寄存数据在时钟沿。

Solution 1

Include all possible cases in the case statement

Verilog

always @ (SEL or DIN1 or DIN2)
 
begin
 
case (SEL)
 
2'b00 : DOUT
2'b01 : DOUT
 
2'b10 : DOUT
endcase
end

VHDL

process (SEL, DIN1, DIN2)
 
begin
 
case SEL is
 
when "00" => DOUT
 
when "01" => DOUT
 
when "10" => DOUT
 
end case;
 
end process;

These two examples create latches because there is no provision for the

case when SEL = "11." To eliminate the latches, add another entry to deal

with this possibility.

Verilog

2'b11 : DOUT

VHDL

when "11" => DOUT

Using the "DEFAULT" (Verilog) or "WHEN OTHERS" (VHDL) clause always works,

but this can create extraneous logic. This is always the safest

methodology, but might produce a larger and slower design since any

unknown state has logic that is needed to bring it to a known state.

Solution 2

Assign to all the same outputs in each case.

Verilog

always @ (SEL or DIN1 or DIN2)
 
begin
 
case (SEL)
 
2'b00 : DOUT
2'b01 : DOUT
 
2'b10 : DOUT
2'b11 :
 
begin
 
DOUT
 
TEMP
 
end
 
endcase
 
end

VHDL

process (SEL, DIN1, DIN2)
 
begin
 
case SEL is
 
when "00" => DOUT
 
when "01" => DOUT
 
when "10" => DOUT
 
when "11" =>
 
DOUT
 
TEMP
 
end case;
 
end process;

These examples infer latches because the "11" case assigns two outputs,

while the others assign only one. Looking at this case from TEMP's point

of view, only one of four possible cases are specified, so it is

incomplete. You can avoid this situation by assigning values to the exact

same list of outputs for each case.

Solution 3

Make sure any "if / else if" statements have a concluding "else" clause:

VHDL:

process (ge, din)
 
begin
 
if (ge = '1') then
 
dout_a
 
else
 
dout_a
 
"else" statement.
 
end if;
 
end process;

Verilog:

always @(ge or din)
 
if (ge) dout_a
 
else dout_a
 
statement.

在不影响电路功能的情况下，要写完整的 if--else 语句。（对于时钟沿触发时，是不要 else

的)

---

ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not

placed at an optimal clock IOB / clock site pair. The clock component is

placed at site . The IO component is placed at site

. This will not allow the use of the fast path between the IO and the Clock buffer. If

this sub optimal condition is acceptable for this design, you may use the

CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a

WARNING and allow your design to continue. However, the use of this override is highly

discouraged as it may lead to very poor timing results. It is recommended that this error

condition be corrected in the design. A list of all the COMP.PINs used in this clock

placement rule is listed below. These examples can be used directly in the .ucf file to

override this clock rule. < NET "Ref_Clk_p" CLOCK_DEDICATED_ROUTE = FALSE; >

解决方法： CLK16_inst 和 Ref_Clk 只都用 BUFG，或都用 IBUFG.(个人验证解决问题，但

不保证一定解决问题)

---

WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp

Flash_rst_n is set but the tri state is not configured. Your problem is in the source code,not your constraints. It's complainingthat you don't ever tristate the signal, either because your equations don't have a tristate term or because that term has been optimised away.

就是非输入加上拉后，没有配置三态。这是程序的出错，不关 constraints。