kintex/kintex Ultrascale DDR3 设计注意事项_ultralscale系列fpga ddr3硬件设计

kintex 系列

1. 参考手册ug586；

2.FPGA DDR3内部走线本身有偏移，需要通过PCB走线来补偿，参考ug586 page196；

   For example, to obtain the package delay information for the 7 series FPGA，XC7K160T-FF676, this command should be issued:
        link_design -part xc7k160tfbg676
        write_csv flight_time

These rules indicate the maximum electrical delays between DDR3 SDRAM signals:
• The maximum electrical delay between any DQ or DM and its associated DQS/DQS# mustbe ≤ ±5 ps.

• The maximum electrical delay between any address and control signals and thecorresponding CK/CK# must be ≤ ±25 ps, with 8 ps being the optimal target.

• CK/CK# signals must arrive at each memory device after the DQS/DQS# signals. The skew allowed between CK/CK# and DQS/DQS# must be bounded between 0 and
1,600 ps. The recommended skew between CK/CK# and DQS/DQS# is 150 ps to 1,600 ps for components/UDIMMs and for RDIMMs it is 450 ps to 750 ps. For DIMM
modules, the total CK/CK# and DQS/DQS# propagation delays from the FPGA to the memory components on the DIMM must be accounted for when designing to this requirement.

• CK/CK# must arrive after DQS/DQS# at each memory component to ensure calibration
can align DQS/DQS# to the correct CK/CK# clock cycle. Write Calibration failures are  seen if this specification is violated.

The specified DQ to DQS skew limit can be increased if the memory interface is not operated at the maximum frequency. Table 1-67 indicates the relaxed skew limit (±) for these cases.The vertical axis is the bit rate in Mb/s. The first column is the FPGA maximum rate, check the data sheet to determine this maximum rate. The second column is the actual speed the memory system is operating at. The horizontal axis is the DDR3 SDRAM component speed rating.

3.输入时钟先经过 ibufds，建议加一级 bufg；

4. Internal V REF Selection – Internal V REF can be used for data group bytes to allow the
use of the V REF pins for normal I/O usage. Internal V REF should only be used for data
rates of 800 Mb/s or below.

---  如果速率高达1600Mb/s   VREF一定要比较干净，只连接FPGA DDR3 Vref

---  DQ\DQS相关的BANK不需要外接的Vref（DDR3 SDRAM颗粒输出不需要），ADDR等控制信号BANK需要接Vref（DDR3 SDRAM颗粒输入需要）；

5.输入时钟必须与DDR bank在同一列，最好分配在address/control bank

6.VCCAUX_IO_G# （Kintex-7 and Virtex-7）低速模式支持1.8V或者2.0V，高速模式必须2.0V，建议直接连接2.0V 保险；

7. DDR3 SDRAM效率较好的情况大概能做到80%-90%之间，从以下几点考虑提供效率

1.尽量较少bank切换；  2.Burst长度尽量增到最大值；3.尽量减少读写切换次数；4.一次burst 不要跨行 

1. Activation time and Precharge time when changing to new banks/rows or changing rows with in the same bank.- Soif you reduce row change, this can remove tRCD and tRP.

2. Send continuous write or read commands -Maintaining tCCD timing.

3. Minimize write to read and read to write command changeover - Write recovery time to change to read accesses,bus turnaround time to change from read to write

4. Set a proper refresh interval.   参考：AR# 63234

kintex Ultrascale 系列

1. kintex Ultrascale 支持DDR3/DDR4 SDRAM

2.PCB部分主要参考 ug583-ultrascale-pcb-design.pdf

3.PCB走线主要关注FPGA晶源到SDRAM颗粒走线等长，

4.SDRAM颗粒内部走线延迟差值没有明确数据，以DDR速度等级来区分，比如下表Table A-1 Memory Component 2133 Mb/s

5.Kintex ultrascale FPGA 封装比较大，晶原到管脚走线差距较大，project Maneger -> Open Synthesized ->I/O Planing ->I/O界面右键export I/O Port 如下图一

图一：获取FPGA内部管脚到晶原走线延迟（单位ps） 图二：FPGA运行速率与PCB走线等长要求

6.如果系统时钟从其他bank输入，添加CLOCK_DEDICATED_ROUTE约束 参考ch.11 clock TXPLL

If the MMCM is driven by the GCIO pin of the other bank, then the
CLOCK_DEDICATED_ROUTE constraint with value "BACKBONE" must be set on the net that
is driving MMCM or on the MMCM input. Setting up the CLOCK_DEDICATED_ROUTE
constraint on the net is preferred. But when the same net is driving two MMCMs, the
CLOCK_DEDICATED_ROUTE constraint must be managed by considering which MMCM
needs the BACKBONE route.
In such cases, the CLOCK_DEDICATED_ROUTE constraint can be set on the MMCM input. To
use the "BACKBONE" route, any clock buffer that exists in the same CMT tile as the GCIO
must exist between the GCIO and MMCM input. The clock buffers that exists in the I/O CMT
are BUFG, BUFGCE, BUFGCTRL, and BUFGCE_DIV. So LPDDR3 SDRAM instantiates BUFG
between the GCIO and MMCM when the GCIO pins and MMCM are not in the same bank
(see Figure 11-1).
If the GCIO pin and MMCM are allocated in different banks, LPDDR3 SDRAM generates
CLOCK_DEDICATED_ROUTE constraints with value as "BACKBONE." If the GCIO pin and
MMCM are allocated in the same bank, there is no need to set any constraints on the
MMCM input.
Similarly when designs are generated with System Clock Configuration as a No Buffer
option, you must take care of the "BACKBONE" constraint and the BUFG/BUFGCE/
BUFGCTRL/BUFGCE_DIV between GCIO and MMCM if GCIO pin and MMCM are allocated in
different banks. LPDDR3 SDRAM does not generate clock constraints in the XDC file for No
Buffer configurations and you must take care of the clock constraints for No Buffer
configurations. For more information on clocking, see the UltraScale Architecture Clocking
Resources User Guide (UG572) [Ref 8].
XDC syntax for CLOCK_DEDICATED_ROUTE constraint is given here:
For LPDDR3:
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */
u_ddr_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1}]