【zynq嵌入式设计一】系统搭建（1）_vivado zynq嵌入式开发

 整体硬件系统的搭建

1. 硬件部分

        1）主控选型

        使用的单片机为zynq7020，其vivado端配置选型如下：

        摄像头选型为淘宝双目ov5640模块，在预研阶段用现成的模块，后续可以进一步绘制pcb或者使用单独的更小巧的模块。

        主控zynq的引脚接线PCB如图所示：

（初稿，在后续会进行修改，具体引脚规则全部参照zynq的pin.xdc文件）

        2）摄像头模块选型（资料详见文档1）

        测试实验中用此款摄像头的单镜头测试。

        模块的io口配置如图：

         因为仅用一个摄像头，因此cmos1系列的io口需要占用，同时额外的io口可以用来进行其他的配置。

        在zynq上io口资源配置如下：

set_property PACKAGE_PIN L16 [get_ports cmos_pclk]
set_property PACKAGE_PIN H16 [get_ports cmos_href]
set_property PACKAGE_PIN D18 [get_ports cmos_vsync]
set_property PACKAGE_PIN H17 [get_ports cmos_rst_n]=
set_property PACKAGE_PIN F17 [get_ports {cmos_data[9]}]
set_property PACKAGE_PIN F16 [get_ports {cmos_data[8]}]
set_property PACKAGE_PIN E18 [get_ports {cmos_data[7]}]
set_property PACKAGE_PIN E19 [get_ports {cmos_data[6]}]
set_property PACKAGE_PIN B19 [get_ports {cmos_data[5]}]
set_property PACKAGE_PIN D19 [get_ports {cmos_data[4]}]
set_property PACKAGE_PIN G15 [get_ports {cmos_data[3]}]
set_property PACKAGE_PIN A20 [get_ports {cmos_data[2]}]
set_property PACKAGE_PIN E17 [get_ports {cmos_data[1]}]
set_property PACKAGE_PIN D20 [get_ports {cmos_data[0]}]
set_property PACKAGE_PIN L17 [get_ports {emio_sccb_tri_io[0]}]
set_property PACKAGE_PIN H15 [get_ports {emio_sccb_tri_io[1]}]

        在实际情况中，因为仅使用其中一部分引脚，保证不占用其他资源，将此处的排针引出单独的排针，进行数据的处理，引出同样2×20P的排针如下：

         3）俯仰角传感器选型（详见文档二）

        对于俯仰角的测量，选用霍尔元件进行测试。 

        每个霍尔元件需要5v供电，GND接地，同时需要一根信号线，八通道数据一共八根信号线与AD7606采集模块的八根信号线相连即可。

       4）采集模块选型（详见文档三）

        对于俯仰角信号需要用霍尔传感器进行测试，霍尔传感器为模拟信号，因此需要通过AD芯片进行数据的采集，此处主要使用AD7606芯片，芯片引脚配置如下：

set_property PACKAGE_PIN N17 [get_ports {ad_os[1]}]
set_property PACKAGE_PIN P18 [get_ports {ad_os[0]}]
set_property PACKAGE_PIN R16 [get_ports ad_range]
set_property PACKAGE_PIN T16 [get_ports ad_convstab]
set_property PACKAGE_PIN U17 [get_ports ad_cvb]
set_property PACKAGE_PIN R17 [get_ports {ad_os[2]}]
set_property PACKAGE_PIN W18 [get_ports ad_rd]
set_property PACKAGE_PIN W19 [get_ports ad_reset]
set_property PACKAGE_PIN Y18 [get_ports ad_busy]
set_property PACKAGE_PIN Y19 [get_ports ad_cs]
set_property PACKAGE_PIN Y17 [get_ports ad_vio]
set_property PACKAGE_PIN V18 [get_ports {ad_data[0]}]
set_property PACKAGE_PIN V17 [get_ports {ad_data[1]}]
set_property PACKAGE_PIN Y14 [get_ports {ad_data[2]}]
set_property PACKAGE_PIN W14 [get_ports {ad_data[3]}]
set_property PACKAGE_PIN W16 [get_ports {ad_data[4]}]
set_property PACKAGE_PIN V16 [get_ports {ad_data[5]}]
set_property PACKAGE_PIN R18 [get_ports {ad_data[6]}]
set_property PACKAGE_PIN T17 [get_ports {ad_data[7]}]
set_property PACKAGE_PIN W15 [get_ports {ad_data[8]}]
set_property PACKAGE_PIN V15 [get_ports {ad_data[9]}]
set_property PACKAGE_PIN R14 [get_ports {ad_data[10]}]
set_property PACKAGE_PIN P14 [get_ports {ad_data[11]}]
set_property PACKAGE_PIN U15 [get_ports {ad_data[12]}]
set_property PACKAGE_PIN U14 [get_ports {ad_data[13]}]
set_property PACKAGE_PIN V13 [get_ports {ad_data[14]}]
set_property PACKAGE_PIN U13 [get_ports {ad_data[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports ad_convstab]
set_property IOSTANDARD LVCMOS33 [get_ports ad_cvb]
set_property IOSTANDARD LVCMOS33 [get_ports ad_vio]
set_property IOSTANDARD LVCMOS33 [get_ports ad_range]
set_property IOSTANDARD LVCMOS33 [get_ports ad_reset]
set_property IOSTANDARD LVCMOS33 [get_ports ad_rd]
set_property IOSTANDARD LVCMOS33 [get_ports ad_cs]
set_property IOSTANDARD LVCMOS33 [get_ports ad_busy]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_os[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[*]}]
set_property PACKAGE_PIN Y16 [get_ports first_data]
set_property IOSTANDARD LVCMOS33 [get_ports first_data]

        5）SPI通信的加速度计模块（详见文档4）

        其主要普通八脚排针即可控制其信号，因此在PCB设计上仅需使用官方库中的八脚排针即可，要将其固定在中心位置，方便对初始数据的采集和存储。

        其与ZYNQ的接线方式详见下述代码。

        其中io0对应SDO；io1对应SDA；ss表示片选信号cs。

        其中ss1，ss2为CS片选信号的必备引脚，不配置程序会产生bug，因此配置对应引脚悬空，占用此两个引脚不进行其他的操作。

set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_io0_io]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_io1_io]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_sck_io]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_ss1_o]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_ss2_o]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_ss_io]
set_property PACKAGE_PIN W13 [get_ports SPI_0_sck_io]
set_property PACKAGE_PIN T15 [get_ports SPI_0_ss_io]
set_property PACKAGE_PIN T10 [get_ports SPI_0_ss1_o]
set_property PACKAGE_PIN T11 [get_ports SPI_0_ss2_o]
set_property PACKAGE_PIN U12 [get_ports SPI_0_io0_io]
set_property PACKAGE_PIN V12 [get_ports SPI_0_io1_io]

        6）IMU模块

        IMU模块的数据主要通过PS端的串口进行通信，因此占用引脚一共四个。

        对应引脚为：

set_property PACKAGE_PIN T12 [get_ports UART_1_rxd]
set_property PACKAGE_PIN T14 [get_ports UART_1_txd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_txd]

        应该预留VCC和GND引脚负责给设备供电。

        7)磁力计传感器

        磁力计传感器模块还在测试中，在后续将配置其储存引脚，将在下一篇博客中记录。

以下是整体的xdc文件：

set_property PACKAGE_PIN L16 [get_ports cmos_pclk]
set_property PACKAGE_PIN H16 [get_ports cmos_href]
set_property PACKAGE_PIN D18 [get_ports cmos_vsync]
set_property PACKAGE_PIN H17 [get_ports cmos_rst_n]
 
 
set_property PACKAGE_PIN F17 [get_ports {cmos_data[9]}]
set_property PACKAGE_PIN F16 [get_ports {cmos_data[8]}]
set_property PACKAGE_PIN E18 [get_ports {cmos_data[7]}]
set_property PACKAGE_PIN E19 [get_ports {cmos_data[6]}]
set_property PACKAGE_PIN B19 [get_ports {cmos_data[5]}]
set_property PACKAGE_PIN D19 [get_ports {cmos_data[4]}]
set_property PACKAGE_PIN G15 [get_ports {cmos_data[3]}]
set_property PACKAGE_PIN A20 [get_ports {cmos_data[2]}]
set_property PACKAGE_PIN E17 [get_ports {cmos_data[1]}]
set_property PACKAGE_PIN D20 [get_ports {cmos_data[0]}]
 
 
set_property IOSTANDARD LVCMOS33 [get_ports cmos_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports cmos_pclk]
set_property IOSTANDARD LVCMOS33 [get_ports cmos_vsync]
set_property IOSTANDARD LVCMOS33 [get_ports cmos_href]
set_property IOSTANDARD LVCMOS33 [get_ports {cmos_data[*]}]
 
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets cmos_pclk_IBUF_BUFG]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets cmos_pclk_IBUF]
 
 
set_property PACKAGE_PIN U18 [get_ports hdmi_tx_clk_p]
set_property PACKAGE_PIN V20 [get_ports hdmi_tx_chn_b_p]
set_property PACKAGE_PIN T20 [get_ports hdmi_tx_chn_g_p]
set_property PACKAGE_PIN N20 [get_ports hdmi_tx_chn_r_p]
 
set_property IOSTANDARD TMDS_33 [get_ports hdmi_tx_chn_r_p]
set_property IOSTANDARD TMDS_33 [get_ports hdmi_tx_chn_g_p]
set_property IOSTANDARD TMDS_33 [get_ports hdmi_tx_chn_b_p]
set_property IOSTANDARD TMDS_33 [get_ports hdmi_tx_clk_p]
 
set_property IOSTANDARD LVCMOS33 [get_ports {emio_sccb_tri_io[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {emio_sccb_tri_io[0]}]
set_property PACKAGE_PIN L17 [get_ports {emio_sccb_tri_io[0]}]
set_property PACKAGE_PIN H15 [get_ports {emio_sccb_tri_io[1]}]
 
 
 
#################### AD7606 on Z7_Lite JP1 ####################
set_property PACKAGE_PIN N17 [get_ports {ad_os[1]}]
set_property PACKAGE_PIN P18 [get_ports {ad_os[0]}]
set_property PACKAGE_PIN R16 [get_ports ad_range]
set_property PACKAGE_PIN T16 [get_ports ad_convstab]
set_property PACKAGE_PIN U17 [get_ports ad_cvb]
set_property PACKAGE_PIN R17 [get_ports {ad_os[2]}]
set_property PACKAGE_PIN W18 [get_ports ad_rd]
set_property PACKAGE_PIN W19 [get_ports ad_reset]
set_property PACKAGE_PIN Y18 [get_ports ad_busy]
set_property PACKAGE_PIN Y19 [get_ports ad_cs]
set_property PACKAGE_PIN Y17 [get_ports ad_vio]
 
set_property PACKAGE_PIN V18 [get_ports {ad_data[0]}]
set_property PACKAGE_PIN V17 [get_ports {ad_data[1]}]
set_property PACKAGE_PIN Y14 [get_ports {ad_data[2]}]
set_property PACKAGE_PIN W14 [get_ports {ad_data[3]}]
set_property PACKAGE_PIN W16 [get_ports {ad_data[4]}]
set_property PACKAGE_PIN V16 [get_ports {ad_data[5]}]
set_property PACKAGE_PIN R18 [get_ports {ad_data[6]}]
set_property PACKAGE_PIN T17 [get_ports {ad_data[7]}]
 
set_property PACKAGE_PIN W15 [get_ports {ad_data[8]}]
set_property PACKAGE_PIN V15 [get_ports {ad_data[9]}]
set_property PACKAGE_PIN R14 [get_ports {ad_data[10]}]
set_property PACKAGE_PIN P14 [get_ports {ad_data[11]}]
set_property PACKAGE_PIN U15 [get_ports {ad_data[12]}]
set_property PACKAGE_PIN U14 [get_ports {ad_data[13]}]
set_property PACKAGE_PIN V13 [get_ports {ad_data[14]}]
set_property PACKAGE_PIN U13 [get_ports {ad_data[15]}]
 
set_property IOSTANDARD LVCMOS33 [get_ports ad_convstab]
set_property IOSTANDARD LVCMOS33 [get_ports ad_cvb]
set_property IOSTANDARD LVCMOS33 [get_ports ad_vio]
set_property IOSTANDARD LVCMOS33 [get_ports ad_range]
set_property IOSTANDARD LVCMOS33 [get_ports ad_reset]
set_property IOSTANDARD LVCMOS33 [get_ports ad_rd]
set_property IOSTANDARD LVCMOS33 [get_ports ad_cs]
set_property IOSTANDARD LVCMOS33 [get_ports ad_busy]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_os[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data[*]}]
 
 
#set_property PACKAGE_PIN P16 [get_ports key_init]
#set_property IOSTANDARD LVCMOS33 [get_ports key_init]
 
 
set_property PACKAGE_PIN Y16 [get_ports first_data]
set_property IOSTANDARD LVCMOS33 [get_ports first_data]
 
 
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_io0_io]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_io1_io]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_sck_io]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_ss1_o]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_ss2_o]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_0_ss_io]
set_property PACKAGE_PIN W13 [get_ports SPI_0_sck_io]
set_property PACKAGE_PIN T15 [get_ports SPI_0_ss_io]
set_property PACKAGE_PIN T10 [get_ports SPI_0_ss1_o]
set_property PACKAGE_PIN T11 [get_ports SPI_0_ss2_o]
set_property PACKAGE_PIN U12 [get_ports SPI_0_io0_io]
set_property PACKAGE_PIN V12 [get_ports SPI_0_io1_io]
 
 
set_property PACKAGE_PIN T12 [get_ports UART_1_rxd]
set_property PACKAGE_PIN T14 [get_ports UART_1_txd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_txd]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]