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- module top(
- input signed [2:0] a,
- input signed [2:0] b,
- output signed [3:0] out
- );
- assign out=a+b;
- endmodule
- module tb(
-
- );
- reg signed [2:0]a;
- reg signed [2:0]b;
- wire signed [3:0]out;
- initial begin
- a=-2; b=-4;
- #20 a=3;b=3;
- #30 a=-4;b=3;
- #10 a=-2;b=3;
- #20 a=-4;b=-4;
- #10 a=-3;
- #50 a=4; //无效的 依然为-4 但不会报错
- end
- top tbtop(a,b,out);
- endmodule
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