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参考野火例程
实现呼吸灯即要调整led亮的占比时间,完成视觉上看起来由灭到亮或者由亮到灭的过程。
design code:
`timescale 1ns / 1ps // // Company: // Engineer: // // Create Date: 2024/04/13 09:31:22 // Design Name: // Module Name: breath_led // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // // module breath_led#( parameter CNT_1US = 6'd49, parameter CNT_1MS = 10'd999, parameter CNT_1S = 10'd999 ) ( input sys_clk, input sys_rst_n, output reg led ); reg [5:0] cnt_1us;//1us内灯全灭或全亮 reg [9:0] cnt_1ms;//1ms的1000个us,cnt_1s是多少就有多少个us亮 reg [9:0] cnt_1s;//1s内的第几个ms reg led_state;//0:从灭到亮;1:从亮到灭,用于计算cnt_1s是加还是减 //us计数 always @(posedge sys_clk or negedge sys_rst_n) begin if(sys_rst_n == 1'b0) cnt_1us <= 6'b0; else if(cnt_1us == CNT_1US) cnt_1us <= 6'b0; else cnt_1us <= cnt_1us + 1'b1; end //ms计数 always @(posedge sys_clk or negedge sys_rst_n) begin if(sys_rst_n == 1'b0) cnt_1ms <= 10'b0; else if(cnt_1us == CNT_1US && cnt_1ms == CNT_1MS)//这里注意一定是同时满足才清零,下面的判定条件同理 cnt_1ms <= 10'b0; else if(cnt_1us == CNT_1US) cnt_1ms <= cnt_1ms + 1'b1; end //s计数 always @(posedge sys_clk or negedge sys_rst_n) begin if(sys_rst_n == 1'b0) cnt_1s <= 10'b0; else if(cnt_1us == CNT_1US && cnt_1ms == CNT_1MS && led_state == 1'b0) cnt_1s <= cnt_1s + 1'b1; else if(cnt_1us == CNT_1US && cnt_1ms == CNT_1MS && led_state == 1'b1) cnt_1s <= cnt_1s - 1'b1; end //state转换 always @(posedge sys_clk or negedge sys_rst_n) begin if(sys_rst_n == 1'b0) led_state <= 1'b0; else if(cnt_1us == CNT_1US && cnt_1ms == CNT_1MS && cnt_1s == CNT_1S) led_state <= 1'b1; else if(cnt_1us == 6'b0 && cnt_1ms == 10'b0 && cnt_1s == 10'b0) led_state <= 1'b0; else led_state <= led_state; end //led输出逻辑 always @(posedge sys_clk or negedge sys_rst_n)begin if(sys_rst_n == 1'b0) led <= 1'b1; else if(cnt_1ms < cnt_1s)//当前是第几个ms则该ms内就有多少个us是亮的 led <= 1'b0; else led <= 1'b1; end endmodule
simulation code
`timescale 1ns / 1ps // // Company: // Engineer: // // Create Date: 2024/04/13 10:17:13 // Design Name: // Module Name: vtf_breath_led_test // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // // module vtf_breath_led_test( ); reg sys_clk; reg sys_rst_n; wire led; initial begin sys_clk = 1'b0; sys_rst_n <= 1'b0; #20 sys_rst_n <= 1'b1; end always #10 sys_clk <= ~sys_clk; breath_led #( .CNT_1US(1'b1), .CNT_1MS(5'd19), .CNT_1S(5'd19) ) bled( .sys_clk(sys_clk), .sys_rst_n(sys_rst_n), .led(led) ); endmodule
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