用非阻塞语句描述的LFSR

lfsrn1.v

module lfsrn1 (q3, q2,q1,n1,clk, pre_n);
      output q3,q2,q1,n1;
      input  clk, pre_n;
      reg    q3, q2, q1;
      wire   n1;
 
      assign n1 = q1 ^ q3;
 
      always @(posedge clk or negedge pre_n)
        if (!pre_n) begin
          q3 <= 1'b1;
          q2 <= 1'b1;
          q1 <= 1'b1;
        end
        else begin
          q3 <= q2;
          q2 <= n1;
          q1 <= q3;
        end
    endmodule

lfsrn1.vt

`timescale 1 ns/ 100 ps
module lfsrn1_vlg_tst();
// constants                                           
// general purpose registers
 
// test vector input registers
reg clk;
reg pre_n;
// wires                                               
wire q3,q2,q1,n1;
 
// assign statements (if any)                          
lfsrn1 i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.pre_n(pre_n),
	.q3(q3),
	.q2(q2),
	.q1(q1),
	.n1(n1)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
  pre_n=1;
#10 pre_n=0;
#10 pre_n=1;
 #100 $stop; 
// --> end                                             
                     
end  
 initial                                                 
begin
  clk<=0;
forever #5 clk=~clk; 
end                                              
endmodule
 

仿真波形图：