小梅哥Xilinx FPGA学习笔记13——动态数码管显示_数码管显示12fpga

module hex8(
    input Clk,
    input Reset_n,
    input [31:0]Disp_Data,
    output reg [7:0]SEL,
    output reg [7:0]SEG
    );
    
    reg [29:0]cnt_1ms;
    reg Flag_1ms; //每1毫秒切换一个数码管
    reg [2:0]cnt_sel;//位选信号   
    parameter MCNT = 50000-1;
    
    //定时一毫秒
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        cnt_1ms <= 0;
    else if(cnt_1ms == MCNT)
        cnt_1ms <= 0;
    else 
        cnt_1ms <= cnt_1ms + 1;
   
    //产生一个一毫秒到来的高脉冲信号
   always@(posedge Clk or negedge Reset_n)
   if(!Reset_n)
       Flag_1ms <= 0;
   else if(cnt_1ms == MCNT)
       Flag_1ms <= 1;
   else 
       Flag_1ms <= 0;     
   
   //cnt_sel自加逻辑实现（每1毫秒自加一次切换一个数码管）
   always@(posedge Clk or negedge Reset_n)
   if(!Reset_n)
       cnt_sel <= 0;
   else if(Flag_1ms)
       cnt_sel <= cnt_sel + 1;
   else
       cnt_sel <= cnt_sel; 
          
   //数码管的位选择逻辑
   always@(posedge Clk)begin
       case(cnt_sel)
           0: SEL <= 8'b0000_0001;
           1: SEL <= 8'b0000_0010;
           2: SEL <= 8'b0000_0100;
           3: SEL <= 8'b0000_1000;
           4: SEL <= 8'b0001_0000;
           5: SEL <= 8'b0010_0000;
           6: SEL <= 8'b0100_0000;
           7: SEL <= 8'b1000_0000;
           default:SEL <= 8'b0000_0000; 
       endcase
   end
   
   reg [3:0]data_temp;//显示16种数值8 + 4 + 2 + 1+1 = 16，
   //建立一个查找表，表中列出SEG段选信号的各种情况。
   always@(posedge Clk)begin
       case(data_temp)
           0: SEG <= 8'b1100_0000; //0
           1: SEG <= 8'b1111_1001; //1
           2: SEG <= 8'b1010_0100; //2
           3: SEG <= 8'b1011_0000; //3
           4: SEG <= 8'b1001_1001; //4
           5: SEG <= 8'b1001_0010; //5
           6: SEG <= 8'b1000_0010; //6
           7: SEG <= 8'b1111_1000; //7  
           8: SEG <= 8'b1000_0000; //8
           9: SEG <= 8'b1001_0000; //9
           10: SEG <= 8'b1000_1000;//A
           11: SEG <= 8'b1000_0011;//B
           12: SEG <= 8'b1100_0110;//C
           13: SEG <= 8'b1010_0001;//D
           14: SEG <= 8'b1000_0110;//E
           15: SEG <= 8'b1000_1110;//F
           default:SEL <= 8'b1111_1111;//全灭
       endcase
   end
   
   //8路选择器实现逻辑（使用组合逻辑时<=与=无区别）
   always@(*)
		case(cnt_sel)
			0:data_temp <= Disp_Data[3:0];
			1:data_temp <= Disp_Data[7:4];
			2:data_temp <= Disp_Data[11:8];
			3:data_temp <= Disp_Data[15:12];
			4:data_temp <= Disp_Data[19:16];
			5:data_temp <= Disp_Data[23:20];
			6:data_temp <= Disp_Data[27:24];
			7:data_temp <= Disp_Data[31:28];
			default:data_temp = 4'b0000;
		endcase
  
endmodule

//只需要对输入信号赋值
`timescale 1ns / 1ps
module hex8_tb();
 
reg Clk;
reg Reset_n;
reg [31:0]Disp_Data;
wire [7:0]SEL;
wire [7:0]SEG;
 
hex8  hex8(
   .Clk(Clk),
   .Reset_n(Reset_n),
   .Disp_Data(Disp_Data),
   .SEL(SEL),
   .SEG(SEG)
);
 
    initial Clk = 1;
    always #10 Clk = ~Clk;
 
    initial
    begin
    Reset_n = 0;
    Disp_Data = 32'h12345678;
    #201;
    Reset_n = 1;
    #20000000;//延时20ms
    Disp_Data = 32'h9abcdef0;
    #20000000;//延时20ms
    $stop;
    end
endmodule