7系列FPGA内部的block ram资源和原语RAMB18E1深入分析

我基于自己原来的文章：第一篇——赛灵思的block memory generator用户手册pg058翻译和学习(24)， 主要介绍Selectable Memory Algorithm；第二篇——赛灵思的block memory generator用户手册pg058翻译和学习(25)， 主要介绍Table 3-1: Memory Primitives Used Based on Architecture (Supported in Native BMG)，延伸一下，反刍和复盘。

结合csdn上搜到的一篇文章：FPGA-7系列FPGA内部结构值Memory Resources-01-block RAM资源 （作者Vuko-wxh），重新了解blockram的两种资源模块/原语primitives: 36kb和18kb.（这篇是讲block ram的）

引申查到的文章：csdn作者摆渡沧桑 浅谈XILINX FPGA CLB单元之分布式RAM（Distributed RAM Available in SLICEM Only、RAM128X1D、Verilog原语描述），这篇是讲分布式ram的，也就是distributed ram,这里便于理解原语是怎么使用的。这里常用的ram原语是RAM32X1S，比下面举例的RAMB18E1要小）

ug473第一章 7系列FPGA内部的block ram资源
block ram资源模块有两种：36kb和18kb （具体总的block RAM 资源有多少? K7325T总共有16M bit的Block RAM）
每个36kb可以配置成4kx9 2kx18等简单双口模式
每个18kb可以配置成2kx9 1kx18等简单双口模式
原语RAMB18E1这是直接用吗？和图形向导生成IP有什么异同？

Block RAM 库原语
7 系列 FPGA 的 Block RAM 库原语 RAMB18E1 和 RAMB36E1 是所有 Block RAM 配置的基本构建块。其他块 RAM 原语和宏基于这些原语。某些 Block RAM 属性只能使用这些原语之一进行配置（例如，流水线寄存器、级联）。请参见 Block RAM 属性部分。

输入和输出数据总线由 9 位宽度 (8 + 1)、18 位宽度 (16 + 2) 和 36 位宽度 (32 + 4) 配置的两条总线表示。与每个字节相关的第九位可以存储奇偶校验/纠错位或用作附加数据位。第 9 位不执行特定功能。奇偶校验位的单独总线有助于某些设计。但是，其他设计通过将常规数据总线与奇偶校验总线合并来安全地使用 9 位、18 位或 36 位总线。所有位的读/写和存储操作都是相同的，包括奇偶校验位。
图片

附，原语RAMB18E1本身的代码：
K7 verilog 版

/ RAMB18E1  : In order to incorporate this function into the design,

// Verilog  : the following instance declaration needs to be placed

// instance  : in the body of the design code. The instance name

// declaration : (RAMB18E1_inst) and/or the port declarations within the

// code    : parenthesis may be changed to properly reference and

// : connect this function to the design.  All inputs

// : and outputs must be connected.

// <-----Cut code below this line---->

// RAMB18E1: 18K-bit Configurable Synchronous Block RAM

//          Kintex-7

// Xilinx HDL Language Template, version 2017.4

RAMB18E1 #(

// Address Collision Mode: "PERFORMANCE" or "DELAYED_WRITE"

.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),

// Collision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")

.SIM_COLLISION_CHECK("ALL"),

// DOA_REG, DOB_REG: Optional output register (0 or 1)

.DOA_REG(0),

.DOB_REG(0),

// INITP_00 to INITP_07: Initial contents of parity memory array

.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),

// INIT_00 to INIT_3F: Initial contents of data memory array

.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),

// INIT_A, INIT_B: Initial values on output ports

.INIT_A(18'h00000),

.INIT_B(18'h00000),

// Initialization File: RAM initialization file

.INIT_FILE("NONE"),

// RAM Mode: "SDP" or "TDP"

.RAM_MODE("TDP"),

// READ_WIDTH_A/B, WRITE_WIDTH_A/B: Read/write width per port

.READ_WIDTH_A(0),                                                                // 0-72

.READ_WIDTH_B(0),                                                                // 0-18

 .WRITE_WIDTH_A(0),                                                               // 0-18

.WRITE_WIDTH_B(0),                                                               // 0-72

// RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")

.RSTREG_PRIORITY_A("RSTREG"),

.RSTREG_PRIORITY_B("RSTREG"),

// SRVAL_A, SRVAL_B: Set/reset value for output

.SRVAL_A(18'h00000),

.SRVAL_B(18'h00000),

// Simulation Device: Must be set to "7SERIES" for simulation behavior

.SIM_DEVICE("7SERIES"),

// WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")

.WRITE_MODE_A("WRITE_FIRST"),

.WRITE_MODE_B("WRITE_FIRST")

)

RAMB18E1_inst (

// Port A Data: 16-bit (each) output: Port A data

.DOADO(DOADO),                 // 16-bit output: A port data/LSB data

.DOPADOP(DOPADOP),             // 2-bit output: A port parity/LSB parity

// Port B Data: 16-bit (each) output: Port B data

.DOBDO(DOBDO),                 // 16-bit output: B port data/MSB data

.DOPBDOP(DOPBDOP),             // 2-bit output: B port parity/MSB parity

// Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals (read port

// when RAM_MODE="SDP")

.ADDRARDADDR(ADDRARDADDR),     // 14-bit input: A port address/Read address

.CLKARDCLK(CLKARDCLK),         // 1-bit input: A port clock/Read clock

.ENARDEN(ENARDEN),             // 1-bit input: A port enable/Read enable

.REGCEAREGCE(REGCEAREGCE),     // 1-bit input: A port register enable/Register enable

.RSTRAMARSTRAM(RSTRAMARSTRAM), // 1-bit input: A port set/reset

.RSTREGARSTREG(RSTREGARSTREG), // 1-bit input: A port register set/reset

.WEA(WEA),                     // 2-bit input: A port write enable

// Port A Data: 16-bit (each) input: Port A data

.DIADI(DIADI),                 // 16-bit input: A port data/LSB data

.DIPADIP(DIPADIP),             // 2-bit input: A port parity/LSB parity

// Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals (write port

// when RAM_MODE="SDP")

.ADDRBWRADDR(ADDRBWRADDR),     // 14-bit input: B port address/Write address

  .CLKBWRCLK(CLKBWRCLK),         // 1-bit input: B port clock/Write clock

.ENBWREN(ENBWREN),             // 1-bit input: B port enable/Write enable

.REGCEB(REGCEB),               // 1-bit input: B port register enable

.RSTRAMB(RSTRAMB),             // 1-bit input: B port set/reset

.RSTREGB(RSTREGB),             // 1-bit input: B port register set/reset

.WEBWE(WEBWE),                 // 4-bit input: B port write enable/Write enable

// Port B Data: 16-bit (each) input: Port B data

.DIBDI(DIBDI),                 // 16-bit input: B port data/MSB data

.DIPBDIP(DIPBDIP)              // 2-bit input: B port parity/MSB parity

);

// End of RAMB18E1_inst instantiation


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301