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Quartus Ⅱ安装包
链接:https://pan.baidu.com/s/12NbAX8J6XBZ7SQAxSj4H_A
提取码:cokm
主要内容:
1.数字钟系统具有时钟、清零和校准输入信号;
2.在系统时钟信号(1Hz)作用下,能显示时、分、秒;
3.时/分/秒计数器为24进制/60进制/60进制;
4.系统可以对时、分校准。校准信号有两个,一为校准时钟输入,一为校准控制输入;
5.系统具有整点报时功能。当时间为59’58’‘、59’59’'时,系统报时各响一声(低音),持续0.5秒;整点系统响一声(高音),持续1秒;
6.采用原理图输入方式设计数字钟单元电路顶层文件 ;下载测试。
module fenpin(CP,CPout);
input CP;
output CPout;
reg CPout;
reg [31:0]Cout;
reg CP_En;
always @(posedge CP)
begin
Cout<=(Cout == 32'd50000)?32'd0:(Cout+32'd1);
CP_En<=(Cout == 32'd50000)?1'd1:1'd0;
CPout<=CP_En;
end
endmodule
控制器
module kongzhiqi(CPout,CP,S1,S2,RET,Hour,Minute,Second,sound); input CPout,CP,S1,S2,RET; output [5:0] Hour; output [5:0] Minute; output [5:0] Second; output sound; reg [5:0] Hour; reg [5:0] Minute; reg [5:0] Second; reg R1; reg R2,R8,sound; reg [10:0] Cout; reg [31:0] C1; reg Clk_En; reg clk_2000; reg cp_n; reg c_1hz,c_2hz,c_1000hz; reg i; integer n2=25000000; integer h2=25000000; always@(posedge CP) begin C1<=(C1==32'd25000)?32'd0:(C1+32'd1); cp_n<=(Cout==32'd25000)?1'd1:1'd0; clk_2000<=cp_n; end always@(posedge CP) if(h2<n2/2-1)h2=h2+1; else begin c_2hz=~c_2hz; h2=0; end always@(posedge c_2hz) begin if(!i)i=1; else i=0; end always @(posedge CPout) begin if(S1==0) begin R1=1; end if(S2==0) begin R2=1; end if(RET==0) begin R8=1; end Cout=(Cout==32'd1000)?32'd0:(Cout + 32'd1); Clk_En=(Cout==32'd1000)?1'd1:1'd0; if(Clk_En) begin if(R1==1) begin if(Hour<24) Hour=Hour+1; if(Hour==24) begin Hour=0; end R1=0; end if(R2==1) begin if(Minute<60) Minute=Minute+1; if(Minute==60) begin Minute=0; if(Hour<24) Hour=Hour+1; if(Hour==24) begin Hour=0; end end R2=0; end if(Second<60) Second= Second+1; if(Second==60) begin Second=0; if(Minute<60) Minute= Minute+1; if(Minute==60) begin Minute=0; if(Hour<24) Hour=Hour+1; if(Hour==24) begin Hour=0; end end end if(R8==1)//清零 begin Hour=0; Minute=0; Second=0; R8=0; end end end always@(Minute,Second) begin if((Minute==59)&&(Second==58 )&& (i==1)) sound=c_2hz; else if((Minute==59)&&(Second==58 )&&( i==0) ) sound=0; else if((Minute==59)&&(Second==59 )&& (i==1) ) sound=c_2hz; else if((Minute==59)&&(Second==59 )&& (i==0) ) sound=0; //if((Minute==59)&&(Second>57))//整点倒计时 // sound=c_2hz; else if((Minute==0)&&(Second==0)) sound=~clk_2000; else sound=0; end endmodule
显示
module xianshi(CPout,Hour,Minute,Second,SEL,LEDAG); input CPout; input [5:0] Hour,Minute,Second; output SEL; output [6:0]LEDAG; reg [2:0] SEL; reg [6:0] Led; reg [3:0] shi1,ge1,shi2,ge2,shi3,ge3; always @(posedge CPout ) begin shi1=Hour/10; ge1=Hour%10; shi2=Minute/10; ge2=Minute%10; shi3=Second/10; ge3=Second%10; //if(SEL==3'b110)//8 if(SEL==3'b111)//1 //判断位选SEL的值,并将此位,上的值输出到数码管 case(shi1) 4'b0000:Led=7'b0111_111; 4'b0001:Led=7'b0000_110; 4'b0010:Led=7'b1011_011; 4'b0011:Led=7'b1001_111; 4'b0100:Led=7'b1100_110; 4'b0101:Led=7'b1101_101; 4'b0110:Led=7'b1111_101; 4'b0111:Led=7'b0000_111; 4'b1000:Led=7'b1111_111; 4'b1001:Led=7'b1101_111; default:Led=7'b0000_000; endcase //if(SEL==3'b101)//7 if(SEL==3'b000)//2 case(ge1) 4'b0000:Led=7'b0111_111; 4'b0001:Led=7'b0000_110; 4'b0010:Led=7'b1011_011; 4'b0011:Led=7'b1001_111; 4'b0100:Led=7'b1100_110; 4'b0101:Led=7'b1101_101; 4'b0110:Led=7'b1111_101; 4'b0111:Led=7'b0000_111; 4'b1000:Led=7'b1111_111; 4'b1001:Led=7'b1101_111; default:Led=7'b0000_000; endcase if(SEL==3'b100) Led=7'b1000_000; //if(SEL==3'b011)//5 if(SEL==3'b010)//4 case(shi2) 4'b0000:Led=7'b0111_111; 4'b0001:Led=7'b0000_110; 4'b0010:Led=7'b1011_011; 4'b0011:Led=7'b1001_111; 4'b0100:Led=7'b1100_110; 4'b0101:Led=7'b1101_101; 4'b0110:Led=7'b1111_101; 4'b0111:Led=7'b0000_111; 4'b1000:Led=7'b1111_111; 4'b1001:Led=7'b1101_111; default:Led=7'b0000_000; endcase //if(SEL==3'b010)//4 if(SEL==3'b011)//5 case(ge2) 4'b0000:Led=7'b0111_111; 4'b0001:Led=7'b0000_110; 4'b0010:Led=7'b1011_011; 4'b0011:Led=7'b1001_111; 4'b0100:Led=7'b1100_110; 4'b0101:Led=7'b1101_101; 4'b0110:Led=7'b1111_101; 4'b0111:Led=7'b0000_111; 4'b1000:Led=7'b1111_111; 4'b1001:Led=7'b1101_111; default:Led=7'b0000_000; endcase if(SEL==3'b001) Led=7'b1000_000; //if(SEL==3'b000)//2 if(SEL==3'b101)//7 case(shi3) 4'b0000:Led=7'b0111_111; 4'b0001:Led=7'b0000_110; 4'b0010:Led=7'b1011_011; 4'b0011:Led=7'b1001_111; 4'b0100:Led=7'b1100_110; 4'b0101:Led=7'b1101_101; 4'b0110:Led=7'b1111_101; 4'b0111:Led=7'b0000_111; 4'b1000:Led=7'b1111_111; 4'b1001:Led=7'b1101_111; default:Led=7'b0000_000; endcase //if(SEL==3'b111)//1 if(SEL==3'b110)//8 case(ge3) 4'b0000:Led=7'b0111_111; 4'b0001:Led=7'b0000_110; 4'b0010:Led=7'b1011_011; 4'b0011:Led=7'b1001_111; 4'b0100:Led=7'b1100_110; 4'b0101:Led=7'b1101_101; 4'b0110:Led=7'b1111_101; 4'b0111:Led=7'b0000_111; 4'b1000:Led=7'b1111_111; 4'b1001:Led=7'b1101_111; default:Led=7'b0000_000; endcase SEL= SEL + 3'd1; end assign LEDAG=Led; endmodule
顶层原理图
管脚锁定图
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