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AT32F437VM SPI驱动AT7456E OSD芯片

at7456e

        上篇文章讲了BF固件中关于OSD的代码部分,今天来看一下硬件部分。    

        使用AT的芯片配置SPI和OSD芯片通讯。

            

先配置一下AT32F437的时钟:

  1. /**
  2. **************************************************************************
  3. * @file at32f435_437_clock.c
  4. * @brief system clock config program
  5. **************************************************************************
  6. * Copyright notice & Disclaimer
  7. *
  8. * The software Board Support Package (BSP) that is made available to
  9. * download from Artery official website is the copyrighted work of Artery.
  10. * Artery authorizes customers to use, copy, and distribute the BSP
  11. * software and its related documentation for the purpose of design and
  12. * development in conjunction with Artery microcontrollers. Use of the
  13. * software is governed by this copyright notice and the following disclaimer.
  14. *
  15. * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  16. * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  17. * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  18. * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  19. * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  21. *
  22. **************************************************************************
  23. */
  24. /* includes ------------------------------------------------------------------*/
  25. #include "at32f435_437_clock.h"
  26. /**
  27. * @brief system clock config program
  28. * @note the system clock is configured as follow:
  29. * - system clock = (hext * pll_ns)/(pll_ms * pll_fr)
  30. * - system clock source = pll (hext)
  31. * - hext = 8000000
  32. * - sclk = 72000000
  33. * - ahbdiv = 1
  34. * - ahbclk = 72000000
  35. * - apb1div = 2
  36. * - apb1clk = 36000000
  37. * - apb2div = 2
  38. * - apb2clk = 36000000
  39. * - pll_ns = 144
  40. * - pll_ms = 1
  41. * - pll_fr = 16
  42. * @param none
  43. * @retval none
  44. */
  45. void system_clock_config(void)
  46. {
  47. /* enable pwc periph clock */
  48. crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
  49. /* config ldo voltage */
  50. pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V0);
  51. /* set the flash clock divider */
  52. flash_clock_divider_set(FLASH_CLOCK_DIV_2);
  53. /* reset crm */
  54. crm_reset();
  55. /* enable hext */
  56. crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
  57. /* wait till hext is ready */
  58. while(crm_hext_stable_wait() == ERROR)
  59. {
  60. }
  61. /* config pll clock resource
  62. common frequency config list: pll source selected hick or hext(8mhz)
  63. _______________________________________________________________________________________
  64. | | | | | | | | | |
  65. |pll(mhz)| 288 | 252 | 216 | 180 | 144 | 108 | 72 | 36 |
  66. |________|_________|_________|_________|_________|_________|_________|_________________|
  67. | | | | | | | | | |
  68. |pll_ns | 72 | 63 | 108 | 90 | 72 | 108 | 72 | 72 |
  69. | | | | | | | | | |
  70. |pll_ms | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
  71. | | | | | | | | | |
  72. |pll_fr | FR_2 | FR_2 | FR_4 | FR_4 | FR_4 | FR_8 | FR_8 | FR_16|
  73. |________|_________|_________|_________|_________|_________|_________|________|________|
  74. if pll clock source selects hext with other frequency values, or configure pll to other
  75. frequency values, please use the at32 new clock configuration tool for configuration. */
  76. crm_pll_config(CRM_PLL_SOURCE_HEXT, 144, 1, CRM_PLL_FR_16);
  77. /* enable pll */
  78. crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
  79. /* wait till pll is ready */
  80. while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
  81. {
  82. }
  83. /* config ahbclk */
  84. crm_ahb_div_set(CRM_AHB_DIV_1);
  85. /* config apb2clk */
  86. crm_apb2_div_set(CRM_APB2_DIV_2);
  87. /* config apb1clk */
  88. crm_apb1_div_set(CRM_APB1_DIV_2);
  89. /* select pll as system clock source */
  90. crm_sysclk_switch(CRM_SCLK_PLL);
  91. /* wait till pll is used as system clock source */
  92. while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
  93. {
  94. }
  95. /* update system_core_clock global variable */
  96. system_core_clock_update();
  97. }

 osd芯片连接原理图:

 

 

接下来SPI配置:

  1. static void spi_config(void)
  2. {
  3. spi_init_type spi_init_struct;
  4. crm_periph_clock_enable(CRM_SPI2_PERIPH_CLOCK, TRUE);
  5. spi_default_para_init(&spi_init_struct);
  6. spi_init_struct.transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
  7. spi_init_struct.master_slave_mode = SPI_MODE_MASTER;
  8. spi_init_struct.mclk_freq_division = SPI_MCLK_DIV_8;
  9. spi_init_struct.first_bit_transmission = SPI_FIRST_BIT_MSB;
  10. spi_init_struct.frame_bit_num = SPI_FRAME_8BIT;
  11. spi_init_struct.clock_polarity = SPI_CLOCK_POLARITY_LOW;
  12. spi_init_struct.clock_phase = SPI_CLOCK_PHASE_1EDGE;
  13. spi_init_struct.cs_mode_selection = SPI_CS_SOFTWARE_MODE;
  14. spi_init(SPI2, &spi_init_struct);
  15. spi_enable(SPI2, TRUE);
  16. }
  17. /**
  18. * @brief gpio configuration.
  19. * @param none
  20. * @retval none
  21. */
  22. static void gpio_config(void)
  23. {
  24. gpio_init_type gpio_initstructure;
  25. crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE);
  26. /* master sck pin */
  27. gpio_initstructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
  28. gpio_initstructure.gpio_pull = GPIO_PULL_DOWN;
  29. gpio_initstructure.gpio_mode = GPIO_MODE_MUX;
  30. gpio_initstructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
  31. gpio_initstructure.gpio_pins = GPIO_PINS_1;
  32. gpio_init(GPIOD, &gpio_initstructure);
  33. gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE1, GPIO_MUX_6);
  34. /* spi2 miso pin */
  35. gpio_initstructure.gpio_pull = GPIO_PULL_UP;
  36. gpio_initstructure.gpio_pins = GPIO_PINS_3;
  37. gpio_init(GPIOD, &gpio_initstructure);
  38. gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE3, GPIO_MUX_6);
  39. /* spi2 mosi pin */
  40. gpio_initstructure.gpio_pull = GPIO_PULL_UP;
  41. gpio_initstructure.gpio_pins = GPIO_PINS_4;
  42. gpio_init(GPIOD, &gpio_initstructure);
  43. gpio_pin_mux_config(GPIOD, GPIO_PINS_SOURCE4, GPIO_MUX_6);
  44. gpio_initstructure.gpio_mode = GPIO_MODE_OUTPUT;
  45. gpio_initstructure.gpio_pins = GPIO_PINS_5;
  46. gpio_initstructure.gpio_pull = GPIO_PULL_NONE;
  47. gpio_init(GPIOD, &gpio_initstructure);
  48. gpio_bits_write(GPIOD, GPIO_PINS_5, 0);
  49. }

主要注意下面的点 

 SPI收发函数,因为是全双工模式,所以这里发送和接收在一个函数中。具体可以看上一篇文章说明了为什么要一起做。

  1. /*************************************************************
  2. ** Function name: SPI2SendAndReceviceOneByte
  3. ** Descriptions: 使用全双工模式的spi进行发送同时接收一字节数据
  4. ** Input parameters: None
  5. ** Output parameters: None
  6. ** Returned value: None
  7. ** Remarks: None
  8. *************************************************************/
  9. uint8_t SPI2SendAndReceviceOneByte(uint8_t data){
  10. while(spi_i2s_flag_get(SPI2, SPI_I2S_TDBE_FLAG) == RESET);
  11. spi_i2s_data_transmit(SPI2, MAX7456ADD_STAT);
  12. while(spi_i2s_flag_get(SPI2, SPI_I2S_RDBF_FLAG) == RESET);
  13. return (uint8_t)spi_i2s_data_receive(SPI2);
  14. }

我之前是分开写的,像是下面的样子:发送了两次,接收一次。这样是错误的

 因为第一次是发送数据,所以没接收。但是发现程序只能成功接收一次。

原因:每次发送的同时都会接收数据,如果这次发送完成后,没有将数据读出来。之后的数据就不会覆盖没读出来的数据,导致往后接收失败。

正确写法:

  1. int main(void)
  2. {
  3. uint16_t redata = 0;
  4. system_clock_config();
  5. at32_board_init();
  6. gpio_config();
  7. spi_config();
  8. delay_ms(200);
  9. SEGGER_RTT_printf(0,"Init ok \r\n");
  10. while(1)
  11. {
  12. SPI2SendAndReceviceOneByte(MAX7456ADD_STAT);
  13. redata = SPI2SendAndReceviceOneByte(0xff);
  14. delay_ms(200);
  15. if (redata != 0){
  16. SEGGER_RTT_printf(0,"%d %x\r\n",redata,redata);
  17. }
  18. // delay_us(2);
  19. }
  20. }

贴个实际的spi信号

 

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