Verilog中task使用_verilog task posedge clk

使用Verilog-2001语法，格式更简洁：

Verilog 1995：Using the Task Function, Combine Port List, Type Information, and Task
By combining the port list and type information, the above features are applicable to
functions and tasks as the task below illustrates:

Verilog 1995：声明端口类型和端口方向要分开

task parity_check;
input [15:0] data_in;
output even;
output odd;
wire [15,10] dat_in
wire even, odd;
…
endtask

Verilog 2001 Combined Functions Port List, Data Information, Data Type, and TaskCombining all aspects of port list, data information, data type, and task, the Verilog2001 standard for this example can be written most succinctly as shown below.

task parity_check (
input wire [15:0] data_in,
output wire even,
output wire odd);

task ... nedtask之间必须有begin ...end模块，否则有错：** Error: ....../tb_fifo_lfsr_sc.v(76): BEGIN - END required around task/function statements

如：task push(input [data_w-1:0] din);   尾部必须有分号收尾

Verilog 2001：把端口声明和端口类型在一行内声明，且可以像module一样，参数列表放在一个括号内

testbench中写的FIFO 读写任务：

task push(input [data_w-1:0] din);
begin
wreq = 1;
d = din*2;
@(posedge clk);
#3;
d = {data_w{1'bx}};
wreq = 0;
@(posedge clk);
end
endtask

task pop;
begin
rreq = 1;
@(posedge clk);
#3;
rreq = 0;
#5;
//@(posedge clk);
end
endtask

程序中调用实例：

for(ii=0;ii<50;ii=ii+1) begin
  push(ii);
end

pop();
pop();
pop();
pop();

</pre><pre name="code" class="plain">