序列发生器10010-verilog_8位m序列发生器verilog

module seq_11001_1(input clk,output led);
reg [31:0] divclk_cnt = 0;
reg divclk = 0;
reg q0 = 0;
reg q1 = 0;
reg q2 = 0;
always @ (posedge clk)
begin
	if(divclk_cnt == 25 )
	begin
		divclk = ~divclk;
		divclk_cnt = 0;
	end
	else
	begin
		divclk_cnt = divclk_cnt + 1'b1;
	end
end
assign led = ~q1;
always @ (posedge divclk)
begin
	q0 <= q1&q2;
	q1 <= ~q1&q2|q1&~q2;
	q2 <= ~q0&q2;
end
endmodule
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module sim1;
	reg clk;
	wire led;
	seq_10010_1 uut(
	clk,led
);
initial begin
	clk = 0;
	end
	always #10 clk = ~clk;
endmodule
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