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Xilinx FPGA中HR、HD、HP bank说明_xilinx19hd

xilinx19hd
  HR bank HP bank HD bank
全称 High Range High Performance High Desity
名称 高范围bank 高性能bank 高密度bank
电压范围 1.2~3.3V 1.0~1.8V 1.2~3.3V
接口速率   支持高速接口 支持低速接口
IO pins总数 50 52 24
differential pairs 24 24 12
       

Standard HP I/O banks each have a total of 52 SelectIO. pins, optionally configurable
as (up to) 24 differential pairs.

Standard HD I/O banks each have a total of 24 SelectIO pins, optionally configurable as
(up to) 12 differential pairs.

如HD bank:

Pin Pin Name Memory Byte Group Bank I/O Type Super Logic Region
AE14 IO_L12N_AD0N_44 NA 44 HD NA
AE15 IO_L12P_AD0P_44 NA 44 HD NA
AG15 IO_L11N_AD1N_44 NA 44 HD NA
AF15 IO_L11P_AD1P_44 NA 44 HD NA
AG13 IO_L10N_AD2N_44 NA 44 HD NA
AG14 IO_L10P_AD2P_44 NA 44 HD NA
AF13 IO_L9N_AD3N_44 NA 44 HD NA
AE13 IO_L9P_AD3P_44 NA 44 HD NA
AJ14 IO_L8N_HDGC_AD4N_44 NA 44 HD NA
AJ15 IO_L8P_HDGC_AD4P_44 NA 44 HD NA
AH13 IO_L7N_HDGC_AD5N_44 NA 44 HD NA
AH14 IO_L7P_HDGC_AD5P_44 NA 44 HD NA
AL12 IO_L6N_HDGC_AD6N_44 NA 44 HD NA
AK13 IO_L6P_HDGC_AD6P_44 NA 44 HD NA
AK14 IO_L5N_HDGC_AD7N_44 NA 44 HD NA
AK15 IO_L5P_HDGC_AD7P_44 NA 44 HD NA
AM13 IO_L4N_AD8N_44 NA 44 HD NA
AL13 IO_L4P_AD8P_44 NA 44 HD NA
AP12 IO_L3N_AD9N_44 NA 44 HD NA
AN12 IO_L3P_AD9P_44 NA 44 HD NA
AN13 IO_L2N_AD10N_44 NA 44 HD NA
AM14 IO_L2P_AD10P_44 NA 44 HD NA
AP14 IO_L1N_AD11N_44 NA 44 HD NA
AN14 IO_L1P_AD11P_44 NA 44 HD NA
AF14 VCCO_44 NA 44 NA NA
AJ13 VCCO_44 NA 44 NA NA

 

如HP bank:

Pin Pin Name Memory Byte Group Bank I/O Type Super Logic Region
AE1 IO_L24N_T3U_N11_PERSTN0_65 3U 65 HP NA
AE2 IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65 3U 65 HP NA
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