用JTAG操作ARTIX 7板子时试过的命令: Hi, I am running the 7015 SOM on an V2 carrier board. Vivado 2015.4 I successfully tried some of the examples, provided by Avnet (e.g. the pz_fmc2_valtest to setup the IDT clock synthesizer on the carrier board). I failed, when try to connect the SDK with the target for direct program download and debug run. The FPGA bitfile gets downloaded from the SDK Xilinx tools menu (via jtag platform cable 2), done LED gets on. But then a message came up, which tells, that the JTAG port is not available. Therefore no debug connection is possible. I tried to connect with the Vivado hardware manager, but failed also. Before the FPGA is programmed I can see the devices (DAP + 7015). After programming I need to restart the hw-server. Here is the log :
start_gui
open_hw
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [
