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经常出现如下错误:
Error: M4K memory block WYSIWYG primitive "cc:inst|altsyncram:altsyncram_component|altsyncram_usc1:auto_generated|altsyncram_ate2:altsyncram1|ram_block3a7" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.
修改方法:
在用到cycloeII的器件,用到RAM,ROM时,要设置一下,在菜单ASSIGNMENTS->SETTING->ANALYSIS&SYNHESIS SETTINGS_DEFAULT PATAMETERS,在NAME 栏键入 CYCLONEII_SAFE_WRITE;<br> 在DEFAULT SETTING栏键入 VERIFIED_SAFE 分别按ADD和OK
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