基于FPGA的数字时钟VHDL开发Modelsim仿真_modelsim用vhdl中wait写一段时钟代码

基于AX301板卡，采用VHDL语言开发：
链接：https://pan.baidu.com/s/1M8AuaZpES561eLHnDVqkow
提取码：fqdi

部分参考代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ShuZhiZhong is
	port(
			clk:			in		std_logic;
			reset_n:		in		std_logic;
			mode_sel:			in	std_logic;
			hour_adjust:		in	std_logic;
			min_adjust:			in	std_logic;
			
			
			sm_cs:		out	std_logic_vector(5 downto 0);
			sm_db:		out	std_logic_vector(7 downto 0);
			
			fmq:			out	std_logic;
			led:			out	std_logic
	);
end ShuZhiZhong;

architecture rtl of ShuZhiZhong is

component Cou
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