WARNING: [Labtools 27-3413] vivado报错调试界面无信号无波形解决方法

vivado----fpga硬件调试 (五) ----找不到ila核问题及解决

INFO: [Labtools 27-2302] Device xczu9 (JTAG device index = 0) is programmed with a design that has 2 ILA core(s).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/example_stimulus_inst0/ila_inst' at location 'uuid_41FD5F9F348352C49809B95E968FAEB2' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/example_checking_inst0/ila_inst' at location 'uuid_6B51478F60F05E37813EC1672C3407E4' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/system_wrapper_i/system_i/system_ila_0/inst/ila_lib' at location 'uuid_8C077A2A8ACC5CC2BB3FE9F1AD28CC92' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/system_wrapper_i/system_i/system_ila_1/inst/ila_lib' at location 'uuid_8D89719A73C25B1C852609031899D29D' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/ila_inst' at location 'uuid_BBBF989AD10F59A191B44CF3E0FBBFD2' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'gth1_example_top/GTH_TX_RX_vio_0_inst' at location 'uuid_DE37F6E204CA542FB479630A93889915' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xczu9_0 and the probes file(s) F:/TLK2711_GTH_serial_to_parallel/project/01dma_ps_base_2711/zu_prj/zu_prj.runs/impl_1/top.ltx.
The device design has 2 ILA core(s) and 0 VIO core(s). 0 ILA core(s) and 0 VIO core(s) are matched in the probes file(s).
Resolution: 
1. Reprogram device with the correct programming file and associated probes file(s) OR
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.
open_bd_design {F:/TLK2711_GTH_serial_to_parallel/project/01dma_ps_base_2711/zu_prj/zu_prj.srcs/sources_1/bd/system/system.bd}

个人情况是用了例程ila核在下载程序后可以弹出调试界面信号及波形。查了原因后，我查看了这个设计用的时钟是zynq PS端提供的输出时钟，所以可以使用，满足解释的原因。自己的在这个设计的基础上加了自己的东西后调试界面就什么都没有了。根据时钟原因，猜测是我的时钟用错了，所以不出图形。最后结果是我用simulation试了一下，单纯的仿真一下不下板子也是有问题的，所以根据问题我改了下代码以后，把基础仿真这关过了再下板子后debug核就出来了。下面是查到的原因。

vivado----fpga硬件调试 (五) ----找不到ila核问题及解决_坚持-CSDN博客

用的这个链接的答案，但怕哪天没了，所以复制一下

大概是说设计里没有ILA core，但是debug文件里有ILA core，而且debug probes窗口下什么也没有。但是，我综合后明明插入了debug core呀，而且在约束文件里也自动生成了相关信息，查看schematic，也添加了debug相关的两个元件，为毛program时就是看不到呢？

不知道有没有人遇到过类似的情况，求指点，万分感谢！

解决：

1： VIO 和 ILA 的CLK 有问题。

2： 我查的Xilinx的论坛，貌似也这么说，说是要用free running clock，但我也没弄明白什么样的叫free running clock。我用的就是那些寄存器本来的时钟，如果换个时钟的话，怎么能保证采样不会出问题呢？还是不太明白，能否详细指教？谢谢啦！

       所谓的free running clock就是上电就跑的时钟，而不是依赖某些条件才有的。补充一点，FREE CLOCK的确是要求上电无条件运行