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Xilinx Spartant6 DDR3 IP核的创建_ddr3 memory address map

ddr3 memory address map
新建一个ISE工程,然后创建一个Ip核。

选择MIG Virtex-6的ip,双击。

 

 

1.双击打开IP核设置的界面。 
image_1cvl8p8c0159r19pp16ccs1914esm.png-72.1kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==点击next

 

 

 

 

2.第二个界面 
image_1cvl8sp44shi1oab1dghpdm1s5o13.png-78.5kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==然后点击next

 

 

 

 

3.第三个界面 
image_1cvl90npoq4jfgc3fd1mn810s31g.png-87.5kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==我们这里不勾选,直接next

 

 

 

 

4. 
image_1cvl98duq1rjcuae1d8s16r68gl2a.png-66kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==
FPGA的原理图,由图可知这块板子的DDR3接着FPGA的BANK3 
image_1cvl9567tu7t1dpj4d11iskf6v1t.png-138.1kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw== 
最后IP核的设置 
image_1cvl9chnehord3i1i4b10kk49i3n.png-50.2kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==

 

 

 

 

5.选择DDR3时钟的工作频率 
image_1cvl9jpcshgus4i193j106fpkt44.png-39.4kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw== 
开发板上的DDR3芯片MT41J64M16LA-187E对应上就行。 
image_1cvl9kgeicqj1hsm1l4hud4lnj4h.png-39.3kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw== 
如果你板子上的DDR3芯片型号没有,那么先选择与你板子上DDR3最相近的信号,然后点击Creat custom part 
image_1cvl9n8l51il91k70vje1pp81b365h.png-31.1kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw== 
看你DDR3芯片手册,将这些时序参数写进去。 
填好之后,继续点击NEXT。

 

 

 

 

6.memory options 设置,什么都不用变,直接next 
image_1cvl9st081fhl11sr1mneish187n5u.png-58.7kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==

 

 

 

 

7.选择Memory port的方式。 
image_1cvla6loo4mq1n6e1010k7d1dol6b.png-67.5kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==
先打开MCB的用户手册 
image_1cvla8gdhvbd1lme2bj1f431l726o.png-171kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==
MCB的全称: Memory Controller Block 
他有2个32bit双向的端口和4个32bit单相的端口组成。 
image_1cvlabjgfrg91vtf6v51o5t13ag75.png-41.3kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw== 
image_1cvladlqg1s915m9ll1bgb1irn7i.png-39.4kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==

 

 

Memory Address mapping selection这里我们选择
bank row col这种形式。
image_1cvlaeun6aa01cps1fce1fm01s8j7v.png-35.9kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==

 

 

8.优先级的设置 
image_1cvlal5sn1r2k3d2q511vnd1eob8c.png-46.2kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==
因为我们前面有设置到我们使用了两个64bit的端口,这两个端口是可以同时进行读写的,但是DDR3芯片,一个时间只能读或者写,所以这里就需要有个优先级。 
我们这里保持默认,直接点击next.

 

 

 

 

9. 
image_1cvlb71jl2irnsh1e96kocago99.png-71.5kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==
这块开发板的时钟采用的是单端的时钟 
image_1cvlb825u2s9163rag61n461dsg9m.png-28.4kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw== 
所以这里设置成single-ended 
RZQ和ZIO引脚时钟,看原理图中,有带下拉电阻的引脚一般是为RZQ和ZIO 
image_1cvlb9r9dq1hf91g821l441p1ua3.png-247.4kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==

 

 

 

 

10.之后的设置一路next就行。最后生成的信息 
点击close. 
image_1cvlbce6c1ua1nqdhd9fml15otbi.png-26.4kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==

 

 

生成后再工程目录下的IP核目录下面
image_1cvlbedik1pa0l46d566kle42bv.png-47.6kBwAAACH5BAEKAAAALAAAAAABAAEAAAICRAEAOw==
有mig_39_2这个文件夹。

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