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基于FPGA的数字时钟的设计课设（HUAT）_fpga数字时钟课程设计

作者：从前慢现在也慢 | 2024-07-18 01:23:50

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fpga数字时钟课程设计

 

 

前言

学校黄老师的FPGA的设计课设，最后的课设为数字时钟，实现分时的计数功能，带有整点报时，按键调节的功能，供电子类学生学习和参考。

 

 

一、数字时钟课设目标

l 基本要求

1、能进行正常的时、分、秒计时功能，分别由6个数码管显示24小时、60分钟、60秒钟的计数器显示。

2、能利用实验系统上的按键实现“校时”“校分”功能：

⑴按下“SA”键时，计时器迅速递增，并按24小时循环，计满23小时后回“00”；

⑵按下“SB”键时，计分器迅速递增，并按59分钟循环，计满59分钟后回“00”，但不向“时”进位；

⑷要求按下“SA”、“SB”或“SC”时均不产生数字跳变（SA”、“SB”、“SC”按键是有抖动的，必须对其消除抖动处理）。

3、能利用扬声器做整点报时：

⑴当计时到达59分50秒时开始报时，在59分50秒、52秒、54秒、56秒、58秒鸣叫，鸣叫声频率可定为512Hz；

⑵到达59分60秒时为最后一声整点报时，整点报时频率可定为1024Hz。

4、用层次化设计方法设计该电路，用Verilog语言编写各个功能模块。

5、完成电路设计后，用实验系统下载验证。

l 发挥部分

   要求实现闹铃功能，准确到分钟。用功能仿真的方法验证，可通过观察有关波形确认电路设计是否正确。

二、部分代码

1.clock.v代码的编写

     秒计数器
 

  1. reg  [25:0]  cnt2;
  2. wire     add_cnt2;
  3. wire     end_cnt2;
  4. always@(posedge clk or negedge rst_n)begin //1s计数，可以通过按键更改
  5.  
  6. if(rst_n == 0)
  7. cnt2 <= 0;
  8. else if (add_cnt2)begin
  9.      if(end_cnt2)
  10.         cnt2 <= 0;
  11.      else
  12.         cnt2 <= cnt2 +1;
  13.  end
  14. end
  15.  
  16. assign add_cnt2 = 1;
  17. assign end_cnt2 = add_cnt2 && cnt2 == y-1;//y可以通过按键更改，实现按键调节时钟频率

us计数器
 

  1. reg [8:0]  cnt0;
  2.  
  3. always@(posedge clk or negedge rst_n) //数码管显示
  4.  
  5.   if(rst_n == 0)
  6.   cnt0 <= 0;
  7.   else if (add_cnt0)
  8.   begin
  9.      if(end_cnt0 )
  10.        cnt0 <= 0;
  11.      else
  12.        cnt0 <= cnt0 +1;
  13.     end
  14.     
  15. assign add_cnt0 = 1;
  16. assign end_cnt0 = add_cnt0 && cnt0== TIME_1US-1;//通过短时间的数码管显示，实现动态扫描

数码管显示   对4个数码管进行us级的循环点亮，达到视觉上的暂留
 

  1. reg  [2:0]  cnt1;
  2. wire     add_cnt1;
  3. wire     end_cnt1;
  4.  
  5. always@(posedge clk or negedge rst_n)begin //4个数码管
  6.  
  7. if(rst_n == 0)
  8. cnt1 <= 0;
  9. else if (add_cnt1)begin
  10.      if(end_cnt1)
  11.         cnt1 <= 0;
  12.      else
  13.         cnt1 <= cnt1 +1;
  14.  end
  15.  
  16.        
  17. end
  18.  
  19. assign add_cnt1 = end_cnt0;
  20. assign end_cnt1 = add_cnt1 && cnt1 == 4-1;

数码管动态扫描

  1. always@(posedge clk or negedge rst_n) //动态扫描
  2. begin
  3.     if(rst_n == 1'b0)
  4.     seg_sel <= 4'b111_1;
  5.         else if (cnt1 == 0)
  6.     seg_sel <= 4'b111_0;
  7.         else if (cnt1 == 1)
  8.     seg_sel <= 4'b110_1;
  9.         else if (cnt1 == 2)
  10.     seg_sel <= 4'b101_1;
  11.         else if (cnt1 == 3)
  12.     seg_sel <= 4'b011_1;
  13.     else
  14.     seg_sel <= 4'b111_1;
  15.     
  16. end

数码管选择显示
 

  1. reg [3:0] sel_data;
  2.  
  3. always@(posedge clk or negedge rst_n)  // 选择显示
  4. begin
  5.  
  6.   if(rst_n == 0)
  7.   seg_ment <=8'hc0;
  8.   else if (sel_data==0)
  9.   seg_ment <= 8'hc0;
  10.     else if (sel_data==1)
  11.   seg_ment <= 8'hf9;
  12.     else if (sel_data==2)
  13.   seg_ment <= 8'ha4;
  14.     else if (sel_data==3)
  15.   seg_ment <= 8'hb0;
  16.   else if (sel_data==4)
  17.   seg_ment <= 8'h99;
  18.   else if (sel_data==5)
  19.   seg_ment <= 8'h92;
  20.   else if (sel_data==6)
  21.   seg_ment <= 8'h82;
  22.   else if (sel_data==7)
  23.   seg_ment <= 8'hf8;
  24.   else if (sel_data==8)
  25.   seg_ment <= 8'h80;
  26.   else if (sel_data==9)
  27.   seg_ment <= 8'h90;
  28.     else
  29.     seg_ment <= 8'hc0;
  30. end
  31.  
  32. always@(*)
  33. begin
  34.     
  35.     if (cnt1==0)
  36.      sel_data <= m_g;
  37.     else if (cnt1==1)
  38.      sel_data <= m_s;
  39.     else if (cnt1==2)
  40.      sel_data <= s_g;
  41.     else
  42.      sel_data <= s_s;
  43.      
  44. end

 

分个位 分十位 时个位 时十位
 

  1. reg  [3:0]  m_g;
  2. wire     add_m_g;
  3. wire     end_m_g;
  4. always@(posedge clk or negedge rst_n)begin
  5.  
  6. if(rst_n == 0)
  7. m_g <= 0;
  8.  
  9.  
  10. else if (add_m_g)
  11.    begin
  12.      if(end_m_g)
  13.         m_g <= 0;
  14.     
  15.      else
  16.         m_g <= m_g +1;
  17.    end
  18. else
  19.         m_g <= m_g;
  20.  
  21. end
  22.  
  23. assign add_m_g = end_cnt2;
  24. assign end_m_g = add_m_g && m_g == 10-1;
  25.  
  26.  
  27. reg  [2:0]  m_s;
  28. wire     add_m_s;
  29. wire     end_m_s;
  30. always@(posedge clk or negedge rst_n)begin
  31.  
  32. if(rst_n == 0)
  33. m_s <= 0;
  34. else if (add_m_s)begin
  35.      if(end_m_s)
  36.         m_s <= 0;
  37.         
  38.      else
  39.         m_s <= m_s +1;
  40.  end
  41. end
  42.  
  43. assign add_m_s = end_m_g;
  44. assign end_m_s = add_m_s && m_s == 6-1;
  45.  
  46.  
  47. reg  [3:0]  s_g;
  48. wire     add_s_g;
  49. wire     end_s_g;
  50. always@(posedge clk or negedge rst_n)begin
  51.  
  52. if(rst_n == 0)
  53. s_g <= 0;
  54. else if (add_s_g)
  55. begin
  56.      if(end_s_g)
  57.         s_g <= 0;
  58.      else if (key_in1 == 1'b0)//保证按键按下时位不产生变化
  59.         s_g <= s_g ;
  60.      else
  61.         s_g <= s_g +1;
  62.  end
  64.  else
  65.      s_g <= s_g;
  66. end
  68. assign add_s_g = end_m_s;
  69. assign end_s_g = add_s_g && s_g == x-1;
  71. reg  [1:0]  s_s;
  72. wire     add_s_s;
  73. wire     end_s_s;
  74. always@(posedge clk or negedge rst_n)begin
  76. if(rst_n == 0)
  77. s_s <= 0;
  78. else if (add_s_s)begin
  79.      if(end_s_s)
  80.         s_s <= 0;
  81.      else
  82.         s_s <= s_s +1;
  83.  end
  84. end
  86. assign add_s_s = end_s_g;
  87. assign end_s_s = add_s_s && s_s == 3-1;   
  89. always@(*)
  90. begin
  92. if(s_s==2)
  93. x=4;
  94. else
  95. x=10;
  97. end

上述基本可以达到数码管显示计数的效果

//按键更改频率
 

  1. parameter  TIME_1S = 5000_000_0;
  2. parameter  TIME_1MS = 5000_000;
  3. parameter  TIME_1NS = 5000_00;
  4.  
  5.  
  6. always@(posedge clk or negedge rst_n)
  7.     if(rst_n == 1'b0)
  8.        y <= TIME_1S;
  9.      else if ( key_in1 == 1'b0) //按键1改时钟频率，同时s_g数码管不变
  10.      begin
  11.      
  12.        y=TIME_1MS;
  13.        
  14.      end
  15.      else if (key_in2 == 1'b0)//按键2 改时钟频率，改的更快
  16.      y=TIME_1NS;
  17.      else
  18.      begin
  19.         y <= TIME_1S;
  20.         
  21.         
  22.      end

 

beep报时
 

  1. //beep 计数
  2. reg   [24:0]   cnt;
  3. reg   [2:0]    cnt_500ms;
  4. reg   [17:0]   freq_cnt;
  5. reg   [17:0]   freq_data;
  6. reg   [17:0]   freq_data2;
  7. wire   [16:0]   duty_data1;
  8. wire   [16:0]   duty_data2;
  9.  
  10. // beep 0.5s的计数
  11. always@(posedge clk or negedge rst_n)
  12.     if(rst_n == 1'b0)
  13.        cnt <= 25'd0;
  14.     else if (cnt == CNT_MAX)
  15.         cnt <= 25'd0;
  16.      else
  17.        cnt <= cnt + 25'b1;
  18.  
  19. always@(posedge clk or negedge rst_n)
  20.     if(rst_n == 1'b0)
  21.        cnt_500ms <= 3'd0;
  22.     else if ((cnt_500ms == 3'd6)&&(cnt == CNT_MAX))
  23.        cnt_500ms <= 3'd0;
  24.     else if  (cnt == CNT_MAX)
  25.        cnt_500ms <= cnt_500ms + 3'd1;
  26.     else
  27.        cnt_500ms <= cnt_500ms;
  28.  //频率计数      
  29. always@(posedge clk or negedge rst_n)
  30.     if(rst_n == 1'b0)
  31.        freq_cnt <= 18'd0;
  32.     else if ((freq_cnt == freq_data)||(cnt == CNT_MAX))
  33.        freq_cnt <= 18'd0;
  34.     else
  35.     freq_cnt  <= freq_cnt + 18'd1;
  36.     
  37. always@(posedge clk or negedge rst_n)
  38.     if(rst_n == 1'b0)
  39.     freq_data <= DO;
  40.     else    case(cnt_500ms)
  41.         3'd0:
  42.         begin
  43.         freq_data <= DO;
  44.         freq_data2<= XI;
  45.         end
  47.        
  48.         
  49.       default :
  50.       begin
  51.       freq_data <= DO;
  52.       freq_data2<= XI;
  53.       end
  54.       
  55.     endcase
  56.     
  57.  assign    duty_data1 = freq_data >> 1;
  58.  assign    duty_data2 = freq_data2 >> 1;
  60.   //报时
  61.  always@(posedge clk or negedge rst_n)
  62.     if(rst_n == 1'b0)
  63.         beep <= 1'b0;
  64.     else if ((freq_cnt >= duty_data1)&&(((m_s == 5)&&(m_g== 2))||((m_s == 5)&&
  65.     (m_g ==0))||((m_s == 5)&&(m_g ==4))||((m_s == 5)&&(m_g ==6))||((m_s == 5)&&(m_g ==8))))// 50 52 54 56 58 报时
  66.         beep <= 1'b1;
  67.      else if ((freq_cnt >= duty_data2)&&(((m_s == 0)&&(m_g== 0))))// 正点报时
  68.         beep <= 1'b1;
  69.     else
  70.         beep <= 1'b0;

 

 

2.完整代码

  1. module clock_k_b
  2. (
  3.  
  4.      input   clk,
  5.      input   rst_n,
  6.      input wire key_in1,
  7.      input wire key_in2,
  8.  
  9.      output  reg [3:0] seg_sel,
  10.      output reg [7:0] seg_ment,
  11.      output reg   beep
  12.  
  13. );
  14.  
  15. parameter  TIME_1US = 500;
  16. parameter  TIME_1S = 5000_000_0;
  17. parameter  TIME_1MS = 5000_000;
  18. parameter  TIME_1NS = 5000_00;
  19. parameter  CNT_MAX =25'd24_999_999;
  20. parameter  DO = 18'd190839;
  21. parameter  XI = 18'd101213;
  23. //
  24. reg [25:0] y;
  25. reg [8:0]  cnt0;
  26. reg [3:0]   x;
  27. wire  add_cnt0;
  28. wire  end_cnt0;
  30. //beep 计数
  31. reg   [24:0]   cnt;
  32. reg   [2:0]    cnt_500ms;
  33. reg   [17:0]   freq_cnt;
  34. reg   [17:0]   freq_data;
  35. reg   [17:0]   freq_data2;
  36. wire   [16:0]   duty_data1;
  37. wire   [16:0]   duty_data2;
  39. // beep 0.5s的计数
  40. always@(posedge clk or negedge rst_n)
  41.     if(rst_n == 1'b0)
  42.        cnt <= 25'd0;
  43.     else if (cnt == CNT_MAX)
  44.         cnt <= 25'd0;
  45.      else
  46.        cnt <= cnt + 25'b1;
  48. always@(posedge clk or negedge rst_n)
  49.     if(rst_n == 1'b0)
  50.        cnt_500ms <= 3'd0;
  51.     else if ((cnt_500ms == 3'd6)&&(cnt == CNT_MAX))
  52.        cnt_500ms <= 3'd0;
  53.     else if  (cnt == CNT_MAX)
  54.        cnt_500ms <= cnt_500ms + 3'd1;
  55.     else
  56.        cnt_500ms <= cnt_500ms;
  57.  //频率计数      
  58. always@(posedge clk or negedge rst_n)
  59.     if(rst_n == 1'b0)
  60.        freq_cnt <= 18'd0;
  61.     else if ((freq_cnt == freq_data)||(cnt == CNT_MAX))
  62.        freq_cnt <= 18'd0;
  63.     else
  64.     freq_cnt  <= freq_cnt + 18'd1;
  65.     
  66. always@(posedge clk or negedge rst_n)
  67.     if(rst_n == 1'b0)
  68.     freq_data <= DO;
  69.     else    case(cnt_500ms)
  70.         3'd0:
  71.         begin
  72.         freq_data <= DO;
  73.         freq_data2<= XI;
  74.         end
  75.  
  76.        
  77.         
  78.       default :
  79.       begin
  80.       freq_data <= DO;
  81.       freq_data2<= XI;
  82.       end
  83.       
  84.     endcase
  85.     
  86.  assign    duty_data1 = freq_data >> 1;
  87.  assign    duty_data2 = freq_data2 >> 1;
  89.   //报时
  90.  always@(posedge clk or negedge rst_n)
  91.     if(rst_n == 1'b0)
  92.         beep <= 1'b0;
  93.     else if ((freq_cnt >= duty_data1)&&(((m_s == 5)&&(m_g== 2))||((m_s == 5)&&
  94.     (m_g ==0))||((m_s == 5)&&(m_g ==4))||((m_s == 5)&&(m_g ==6))||((m_s == 5)&&(m_g ==8))))// 50 52 54 56 58 报时
  95.         beep <= 1'b1;
  96.      else if ((freq_cnt >= duty_data2)&&(((m_s == 0)&&(m_g== 0))))// 正点报时
  97.         beep <= 1'b1;
  98.     else
  99.         beep <= 1'b0;   
  100. always@(posedge clk or negedge rst_n)
  101.     if(rst_n == 1'b0)
  102.        y <= TIME_1S;
  103.      else if ( key_in1 == 1'b0) //按键1改时钟频率，同时s_g数码管不变
  104.      begin
  105.      
  106.        y=TIME_1MS;
  107.        
  108.      end
  109.      else if (key_in2 == 1'b0)//按键2 改时钟频率，改的更快
  110.      y=TIME_1NS;
  111.      else
  112.      begin
  113.         y <= TIME_1S;
  114.         
  115.         
  116.      end
  117.        
  118. /*  always@(posedge clk or negedge rst_n)
  119.     if(rst_n == 1'b0)
  120.     begin
  121.         //beep <= 1'b0;
  122.         led <= 1'b1;
  123.     end
  124.     else if (m_s>= 5)
  125.     begin
  126.         //beep <= 1'b1;
  127.         led <= ~led;
  128.     end
  129.     else
  130.         begin     
  131.         //beep <= 1'b0;
  132.         led <= led;
  133.         end */
  134.        
  135. always@(posedge clk or negedge rst_n) //数码管显示
  137.   if(rst_n == 0)
  138.   cnt0 <= 0;
  139.   else if (add_cnt0)
  140.   begin
  141.      if(end_cnt0 )
  142.        cnt0 <= 0;
  143.      else
  144.        cnt0 <= cnt0 +1;
  145.     end
  146.     
  147. assign add_cnt0 = 1;
  148. assign end_cnt0 = add_cnt0 && cnt0== TIME_1US-1;
  150. reg  [2:0]  cnt1;
  151. wire     add_cnt1;
  152. wire     end_cnt1;
  154. always@(posedge clk or negedge rst_n)begin //4个数码管
  156. if(rst_n == 0)
  157. cnt1 <= 0;
  158. else if (add_cnt1)begin
  159.      if(end_cnt1)
  160.         cnt1 <= 0;
  161.      else
  162.         cnt1 <= cnt1 +1;
  163.  end
  164.  
  165.        
  166. end
  168. assign add_cnt1 = end_cnt0;
  169. assign end_cnt1 = add_cnt1 && cnt1 == 4-1;
  171. reg  [25:0]  cnt2;
  172. wire     add_cnt2;
  173. wire     end_cnt2;
  174. always@(posedge clk or negedge rst_n)begin //1s计数，可以通过按键更改
  176. if(rst_n == 0)
  177. cnt2 <= 0;
  178. else if (add_cnt2)begin
  179.      if(end_cnt2)
  180.         cnt2 <= 0;
  181.      else
  182.         cnt2 <= cnt2 +1;
  183.  end
  184. end
  186. assign add_cnt2 = 1;
  187. assign end_cnt2 = add_cnt2 && cnt2 == y-1;
  189. reg [3:0] sel_data;
  191. always@(posedge clk or negedge rst_n)  // 选择显示
  192. begin
  194.   if(rst_n == 0)
  195.   seg_ment <=8'hc0;
  196.   else if (sel_data==0)
  197.   seg_ment <= 8'hc0;
  198.     else if (sel_data==1)
  199.   seg_ment <= 8'hf9;
  200.     else if (sel_data==2)
  201.   seg_ment <= 8'ha4;
  202.     else if (sel_data==3)
  203.   seg_ment <= 8'hb0;
  204.   else if (sel_data==4)
  205.   seg_ment <= 8'h99;
  206.   else if (sel_data==5)
  207.   seg_ment <= 8'h92;
  208.   else if (sel_data==6)
  209.   seg_ment <= 8'h82;
  210.   else if (sel_data==7)
  211.   seg_ment <= 8'hf8;
  212.   else if (sel_data==8)
  213.   seg_ment <= 8'h80;
  214.   else if (sel_data==9)
  215.   seg_ment <= 8'h90;
  216.     else
  217.     seg_ment <= 8'hc0;
  218. end
  219.  
  220.  
  221.  
  222. always@(posedge clk or negedge rst_n) //动态扫描
  223. begin
  224.     if(rst_n == 1'b0)
  225.     seg_sel <= 4'b111_1;
  226.         else if (cnt1 == 0)
  227.     seg_sel <= 4'b111_0;
  228.         else if (cnt1 == 1)
  229.     seg_sel <= 4'b110_1;
  230.         else if (cnt1 == 2)
  231.     seg_sel <= 4'b101_1;
  232.         else if (cnt1 == 3)
  233.     seg_sel <= 4'b011_1;
  234.     else
  235.     seg_sel <= 4'b111_1;
  236.     
  237. end    
  238.  
  239. reg  [3:0]  m_g;
  240. wire     add_m_g;
  241. wire     end_m_g;
  242. always@(posedge clk or negedge rst_n)begin
  243.  
  244. if(rst_n == 0)
  245. m_g <= 0;
  246.  
  247.  
  248. else if (add_m_g)
  249.    begin
  250.      if(end_m_g)
  251.         m_g <= 0;
  252.     
  253.      else
  254.         m_g <= m_g +1;
  255.    end
  256. else
  257.         m_g <= m_g;
  258.  
  259. end
  260.  
  261. assign add_m_g = end_cnt2;
  262. assign end_m_g = add_m_g && m_g == 10-1;
  263.  
  264.  
  265. reg  [2:0]  m_s;
  266. wire     add_m_s;
  267. wire     end_m_s;
  268. always@(posedge clk or negedge rst_n)begin
  269.  
  270. if(rst_n == 0)
  271. m_s <= 0;
  272. else if (add_m_s)begin
  273.      if(end_m_s)
  274.         m_s <= 0;
  275.         
  276.      else
  277.         m_s <= m_s +1;
  278.  end
  279. end
  280.  
  281. assign add_m_s = end_m_g;
  282. assign end_m_s = add_m_s && m_s == 6-1;
  283.  
  284.  
  285. reg  [3:0]  s_g;
  286. wire     add_s_g;
  287. wire     end_s_g;
  288. always@(posedge clk or negedge rst_n)begin
  289.  
  290. if(rst_n == 0)
  291. s_g <= 0;
  292. else if (add_s_g)
  293. begin
  294.      if(end_s_g)
  295.         s_g <= 0;
  296.      else if (key_in1 == 1'b0)
  297.         s_g <= s_g ;
  298.      else
  299.         s_g <= s_g +1;
  300.  end
  302.  else
  303.      s_g <= s_g;
  304. end
  306. assign add_s_g = end_m_s;
  307. assign end_s_g = add_s_g && s_g == x-1;
  309. reg  [1:0]  s_s;
  310. wire     add_s_s;
  311. wire     end_s_s;
  312. always@(posedge clk or negedge rst_n)begin
  314. if(rst_n == 0)
  315. s_s <= 0;
  316. else if (add_s_s)begin
  317.      if(end_s_s)
  318.         s_s <= 0;
  319.      else
  320.         s_s <= s_s +1;
  321.  end
  322. end
  324. assign add_s_s = end_s_g;
  325. assign end_s_s = add_s_s && s_s == 3-1;   
  327. always@(*)
  328. begin
  330. if(s_s==2)
  331. x=4;
  332. else
  333. x=10;
  335. end
  337. /* always@(posedge clk or negedge rst_n)
  338. begin
  339.     if(rst_n == 1'b0)
  340.      sel_data <= 0;
  341.     else if (cnt1==0)
  342.      sel_data <= m_g;
  343.     else if (cnt1==1)
  344.      sel_data <= m_s;
  345.     else if (cnt1==2)
  346.      sel_data <= s_g;
  347.     else if (cnt1==3)
  348.      sel_data <= s_s;
  349.      
  350. end  */
  351.  
  352. always@(*)
  353. begin
  354.     
  355.     if (cnt1==0)
  356.      sel_data <= m_g;
  357.     else if (cnt1==1)
  358.      sel_data <= m_s;
  359.     else if (cnt1==2)
  360.      sel_data <= s_g;
  361.     else
  362.      sel_data <= s_s;
  363.      
  364. end  
  365.  
  366.  
  367.     
  368. endmodule

3.仿真代码

  1. `timescale 1ns/1ns 
  2.  
  3. module tb_clock();
  4.  
  5. parameter  CYCLE = 20;
  6.  
  7. reg clk;
  8. reg rst_n;
  9.  
  10. wire [3:0] seg_sel;
  11. wire [6:0] seg_ment;
  12.  
  13. clock 
  14. #(
  15.     .TIME_1US (100),
  16.     .TIME_1S  (10)
  17. )
  18.  clock_inst
  19. (
  20.      .clk      (clk),
  21.      .rst_n    (rst_n),
  22.      .seg_sel  (seg_sel),
  23.      .seg_ment (seg_ment)
  24. );
  25.  
  26. initial 
  27.     begin 
  28.     clk = 0;
  29.     forever#(CYCLE/2)begin  
  30.      clk=~clk;
  31.     end 
  32.   end
  33.   
  34. initial 
  35.     begin
  36.     #1
  37.     rst_n = 0;
  38.     #(10*CYCLE);
  39.     rst_n = 1;
  40.     end
  41.     
  42.      
  43.  
  44. endmodule

总结

这是暑假自学搞得数字时钟的设计，虽然功能齐全，但是难免有点不完美的地方，也可以通过层次化的设计让代码变得没有这么长，可以通过这一份代码，要是期末课设弄不出来，参考一下也是可以的，免得挂了，功能反正都可以实现。若有更好的点子也可以一起交流学习一下。

 

 

 

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