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基于FPGA的LMS自适应滤波器_fpga lms自适应滤波器

作者：代码探险家 | 2024-07-04 14:24:15

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fpga lms自适应滤波器

在传统的数字滤波器设计中，最重要的就是滤波器的系数。不管是用matlab的fdatool工具实现，还是用别的滤波器系数生成工具产生该系数，过程都是比较麻烦的。而且生成滤波器系数以后，滤波器的幅频响应，相频响应都已经被固定，如果要修改滤波器的参数，必须要从重新对滤波器的系数进行计算和量化并生成coe文件，才可以更改滤波器。所以基于以上原因，可以设计一个自适应的数字滤波器 ，通过计算输出信号和期望信号的误差来进行对滤波器系数的更新。

下面简单介绍一下系数更新算法：

 从上面的公式我们可以看出，下一时刻的滤波器系数是上一个时刻的滤波器系数加步长因子（u）与误差和输入信号的乘积。（步长因子决定了滤波器的收敛情况，通常情况下，步长因子为输入信号的自相关矩阵的特征值分之2）

自适应滤波器的matlab仿真：

下面是对于LMS函数的实现：

  1. function [w,e,yn] = my_LMS(xn,dn)
  2.  
  3. %   输入：
  4. % xn   输入信号       
  5. % dn   理想信号          
  6. % L    迭代次数      
  7. % k    滤波器的阶数   
  8. %   输出：
  9. % w    滤波器的系数矩阵    大小为 k×L  每一列代表一次迭代后的系数
  10. % e    误差信号            大小为 L×1  每一行代表一次迭代后产生的误差
  11. % yn   滤波器的输出信号    
  12.  
  13. %% 参数配置
  14. k=128;              %滤波器阶数
  15. L=length(xn);       %迭代次数=输入信号长度
  16.  
  17. %% 初始化
  18. yn=zeros(1,L);      %初始化滤波输出信号
  19. yn(1:k)=xn(1:k);    %初始化输出信号前k位数据，保证
  20. w=zeros(1,k);       %初始化权重
  21. e=zeros(1,L);       %初始化误差
  22.  
  23. %% 求收敛常数u
  24. fe = max(eig(xn*xn.'));%求解输入xn的自相关矩阵的最大特征值fe,A = eig(B),意为将矩阵B的特征值组成向量A
  25. u = 2*(1/fe);
  26.  
  27. %% 迭代更新滤波器的参数
  28. for i=(k+1):L             %要保证输入延时后的信号有效，所以实际的迭代次数只有（L-k）次，
  29.     XN=xn((i-k+1):(i));   %将输入信号延迟，使得滤波器的每个抽头都有输入
  30.     yn(i)=w*XN';          %计算出滤波器的输出
  31.     e(i)=dn(i)-yn(i);     %得出误差信号
  32.     w=w+u*e(i)*XN;        %迭代更新滤波器的系数
  33. end
  34.  
  35. end

下面便调用上述函数：

要将所生成的正弦波和加噪后的正弦波量化，在后面的vivado中会用到该量化好的数据。

（要注意加噪后的量化信号，有的时候会出现错误（在vivado中无法读取），所以在生成的txt文件中自行修改错误的数据）

  1. clear;
  2. clc;
  3. close all;
  4.  
  5. L=1024;    %信号长度
  6. a=1;       %原始信号幅度
  7. t=1:L;      
  8. dn=a*sin(0.05*pi*t);%原始正弦信号
  9. subplot(411);plot(dn);axis([0,L,-a-1,a+1]);
  10. %fidc= fopen('C:/Users/Lenovo/Desktop/LMS/matlab/sin_data.txt','wt'); //将正弦波信号量化
  11. %for x = 1 : L
  12. %    fprintf(fidc,'%x\n',round((dn+2.12)*58));
  13. %end  
  14. %fclose(fidc); 
  15.  
  16. xn=awgn(dn,1);   %添加信噪比5dB的白高斯噪声
  17.  
  18. subplot(412);plot(xn);axis([0,L,-a-1,a+1]);
  19. title('信号加高斯白噪声后的时域波形');
  20. fidc= fopen('C:/Users/Lenovo/Desktop/LMS/matlab/add_noise_data.txt','wt'); //将加噪正弦波量化
  21. for x = 1 : L
  22.     fprintf(fidc,'%x\n',round((xn+2.12)*58));
  23. end  
  24. fclose(fidc); 
  25.  
  26. [w,e,yn] = my_LMS(xn,dn);%调用滤波算法
  27.  
  28. subplot(413);plot(yn);axis([0,L,-a-1,a+1]);
  29. title('LMS算法自适应滤波后的输出时域波形');
  30.  
  31. subplot(414);plot(e);axis([0,L,-a-1,a+1]);
  32. title('LMS算法自适应滤波后与原始信号误差');

matlab仿真波形：

 从上面的图我们可以看出该自适应滤波器已经完成了滤波。下面开始滤波器的fpga实现：

顶层模块：

  1. module lms_top(
  2.     input clk_i,
  3.     input rst_n_i,
  4.     input signed [15:0] data_in,        //输入待滤波数据
  5.     input signed [15:0] data_ref,       //参考数据
  6.     output signed [15:0] error_o,         //误差
  7.     output signed [31:0] data_o         //输出数据
  8.     );
  9.  
  10.     wire signed [15:0] coef1;
  11.     wire signed [15:0] coef2;
  12.     wire signed [15:0] coef3;
  13.     wire signed [15:0] coef4;
  14.     wire signed [15:0] coef5;
  15.     wire signed [15:0] coef6;
  16.     wire signed [15:0] coef7;
  17.     wire signed [15:0] coef8;
  18.     wire signed [15:0] coef9;
  19.  
  20. fir fir_inst (
  21.       .clk_i (clk_i ),
  22.       .rst_n_i (rst_n_i ),
  23.       .data_in (data_in ),
  24.       .coef1 (coef1 ),
  25.       .coef2 (coef2 ),
  26.       .coef3 (coef3 ),
  27.       .coef4 (coef4 ),
  28.       .coef5 (coef5 ),
  29.       .coef6 (coef6 ),
  30.       .coef7 (coef7 ),
  31.       .coef8 (coef8 ),
  32.       .coef9 (coef9 ),
  33.       .data_o(data_o)
  34.     );
  35.   
  36. error_calcu error_calcu_inst (
  37.       .clk_i (clk_i ),
  38.       .rst_n_i (rst_n_i ),
  39.       .data_in (data_o ), //data_in  data_o
  40.       .data_ref (data_ref ),
  41.       .error_o  ( error_o)
  42.     );
  43.  
  44. coef_update coef_update_inst(
  45.       .clk_i (clk_i ),
  46.       .rst_n_i (rst_n_i ),
  47.       .error_o (error_o ),
  48.       .data_in (data_in ),
  49.       .coef1 (coef1 ),
  50.       .coef2 (coef2 ),
  51.       .coef3 (coef3 ),
  52.       .coef4 (coef4 ),
  53.       .coef5 (coef5 ),
  54.       .coef6 (coef6 ),
  55.       .coef7 (coef7 ),
  56.       .coef8 (coef8 ),
  57.       .coef9 (coef9 )
  58.     );
  59.     
  60. endmodule

FIR滤波器模块：

  1. module fir(
  2.     input                clk_i,
  3.     input                rst_n_i,
  4.     input  signed [15:0] data_in,                       //fir_i,
  5.  
  6.     input signed [15:0] coef1,                          //权值
  7.     input signed [15:0] coef2,
  8.     input signed [15:0] coef3,
  9.     input signed [15:0] coef4,
  10.     input signed [15:0] coef5,
  11.     input signed [15:0] coef6,
  12.     input signed [15:0] coef7,
  13.     input signed [15:0] coef8,
  14.     input signed [15:0] coef9,
  15.  
  16.     output reg [31:0] data_o                   //fir_o        
  17.     );
  18.  
  19.  
  20. reg[15:0] delay_pipeline1 ;//延时模块
  21. reg[15:0] delay_pipeline2 ;
  22. reg[15:0] delay_pipeline3 ;
  23. reg[15:0] delay_pipeline4 ;
  24. reg[15:0] delay_pipeline5 ;
  25. reg[15:0] delay_pipeline6 ;
  26. reg[15:0] delay_pipeline7 ;
  27. reg[15:0] delay_pipeline8 ;
  28. reg[15:0] delay_pipeline9 ;
  29. /*第一级流水，将输入信号进行延时，每到来一个时钟信号，
  30. 便将输入信号保存到delay_pipelin1中，然后将剩下的依次移动一位。*/
  31. always@(posedge clk_i or negedge rst_n_i)
  32.       if(rst_n_i == 1'b0)
  33.                begin
  34.                     delay_pipeline1 <= 16'b0 ;
  35.                     delay_pipeline2 <= 16'b0 ;
  36.                     delay_pipeline3 <= 16'b0 ;
  37.                     delay_pipeline4 <= 16'b0 ;
  38.                     delay_pipeline5 <= 16'b0 ;
  39.                     delay_pipeline6 <= 16'b0 ;
  40.                     delay_pipeline7 <= 16'b0 ;
  41.                     delay_pipeline8 <= 16'b0 ;
  42.                     delay_pipeline9 <= 16'b0 ;
  43.                end
  44.        else begin
  45.                     delay_pipeline1 <= data_in     ;
  46.                     delay_pipeline2 <= delay_pipeline1 ;
  47.                     delay_pipeline3 <= delay_pipeline2 ;
  48.                     delay_pipeline4 <= delay_pipeline3 ;
  49.                     delay_pipeline5 <= delay_pipeline4 ;
  50.                     delay_pipeline6 <= delay_pipeline5 ;
  51.                     delay_pipeline7 <= delay_pipeline6 ;
  52.                     delay_pipeline8 <=delay_pipeline7 ;
  53.                     delay_pipeline9<= delay_pipeline8 ;
  54.                end
  55. //乘积结果保存寄存器
  56. reg signed [31:0] multi_data1 ;
  57. reg signed [31:0] multi_data2 ;
  58. reg signed [31:0] multi_data3 ;
  59. reg signed [31:0] multi_data4 ;
  60. reg signed [31:0] multi_data5 ;
  61. reg signed [31:0] multi_data6 ;
  62. reg signed [31:0] multi_data7 ;
  63. reg signed [31:0] multi_data8 ;
  64. reg signed [31:0] multi_data9 ;
  65.  
  66. //x(n) * h(n-k)
  67. always@(posedge clk_i or negedge rst_n_i) 
  68.       if(rst_n_i == 1'b0) 
  69.       begin                                 
  70.           multi_data1 <= 32'b0 ;
  71.       end
  72.        else begin
  73.           multi_data1 <= delay_pipeline1 * coef1 ; 
  74.        end          
  75. //x(1) * h(1)
  76. always@(posedge clk_i or negedge rst_n_i) 
  77.       if(rst_n_i == 1'b0)                                   
  78.           multi_data2 <= 32'b0 ;
  79.        else
  80.           multi_data2 <= delay_pipeline2 * coef2 ;
  81. //x(2) * h(2)   
  82. always@(posedge clk_i or negedge rst_n_i) 
  83.       if(rst_n_i == 1'b0)                                   
  84.           multi_data3 <= 32'b0 ;
  85.        else
  86.           multi_data3 <= delay_pipeline3 * coef3 ;
  87.   //x(3) * h(3)        
  88. always@(posedge clk_i or negedge rst_n_i) 
  89.       if(rst_n_i == 1'b0)                                   
  90.           multi_data4 <= 32'b0 ;
  91.        else
  92.           multi_data4 <= delay_pipeline4 * coef4 ;
  93. //x(4) * h(4)     
  94.  always@(posedge clk_i or negedge rst_n_i) 
  95.       if(rst_n_i == 1'b0)                                   
  96.           multi_data5 <= 32'b0 ;
  97.        else
  98.           multi_data5 <= delay_pipeline5 * coef5 ;
  99. //x(5) * h(5)   
  100. always@(posedge clk_i or negedge rst_n_i) 
  101.       if(rst_n_i == 1'b0)                                   
  102.           multi_data6 <= 32'b0 ;
  103.        else
  104.           multi_data6 <= delay_pipeline6 * coef6 ;
  105. //x(6) * h(6)          
  106. always@(posedge clk_i or negedge rst_n_i) 
  107.       if(rst_n_i == 1'b0)                                   
  108.           multi_data7 <= 32'b0 ;
  109.        else
  110.           multi_data7 <= delay_pipeline7 * coef7;
  111. //x(7) * h(7)          
  112. always@(posedge clk_i or negedge rst_n_i) 
  113.       if(rst_n_i == 1'b0)                                   
  114.           multi_data8 <= 32'b0 ;
  115.        else
  116.           multi_data8 <= delay_pipeline8 * coef8;
  117. //x(8) * h(8)        
  118. always@(posedge clk_i or negedge rst_n_i) 
  119.       if(rst_n_i == 1'b0)                                   
  120.           multi_data9 <= 32'b0 ;
  121.        else
  122.           multi_data9 <= delay_pipeline9 * coef9 ;
  123. //将乘积累加，累加的结果就是滤波后的信号                                                       
  124. always@(posedge clk_i or negedge rst_n_i)
  125.       if(rst_n_i == 1'b0)                                  
  126.           data_o <= 32'b0;
  127.        else
  128.           data_o <= multi_data1 + multi_data2 + multi_data3 + 
  129.           multi_data4 +multi_data5 + multi_data6 + multi_data7 +
  130.            multi_data8 + multi_data9 ;
  131. endmodule

误差计算模块：

  1. module error_calcu(
  2.     input                clk_i,
  3.     input                rst_n_i,
  4.     input  signed [31:0] data_in,           //滤波完成数据32
  5.     input  signed [15:0] data_ref,          //参考数据
  6.     output signed [15:0] error_o            //误差输出
  7.     );
  8.  
  9.     wire  signed [15:0] error;
  10.  
  11. //延时寄存参考数据
  12.     reg signed [15:0] data_shift1;
  13.     reg signed [15:0] data_shift2;
  14.     reg signed [15:0] data_shift3;
  15.     reg signed [15:0] data_shift4;
  16.     reg signed [15:0] data_shift5;
  17.     reg signed [15:0] data_shift6;
  18.     reg signed [15:0] data_shift7;
  19.     reg signed [15:0] data_shift8;
  20.     reg signed [15:0] data_shift9;
  21.     
  22.     always @(posedge clk_i or negedge rst_n_i) begin
  23.         if(rst_n_i == 1'b0)
  24.         begin
  25.             data_shift1 <= 16'd0;
  26.             data_shift2 <= 16'd0;
  27.             data_shift3 <= 16'd0;
  28.             data_shift4 <= 16'd0;
  29.             data_shift5 <= 16'd0;
  30.             data_shift6 <= 16'd0;
  31.             data_shift7 <= 16'd0;
  32.             data_shift8 <= 16'd0;
  33.             data_shift9 <= 16'd0;
  34.         end
  35.         else begin
  36.             data_shift1 <= data_ref   ;
  37.             data_shift2 <= data_shift1;
  38.             data_shift3 <= data_shift2;
  39.             data_shift4 <= data_shift3;
  40.             data_shift5 <= data_shift4;
  41.             data_shift6 <= data_shift5;
  42.             data_shift7 <= data_shift6;
  43.             data_shift8 <= data_shift7;
  44.             data_shift9 <= data_shift8;
  45.         end
  46.     end
  47.  
  48. assign error = data_in - data_shift9;
  49. assign error_o = error;
  50.  
  51. endmodule

系数更新模块：

  1. module coef_update(                     //系数更新模块
  2.     input               clk_i,
  3.     input               rst_n_i,
  4.     input signed [15:0] error_o,          //误差
  5.     input signed [15:0] data_in,        //待滤波数据
  6.  
  7.     //权值更新
  8.     output reg [15:0] coef1,
  9.     output reg [15:0] coef2,
  10.     output reg [15:0] coef3,
  11.     output reg [15:0] coef4,
  12.     output reg [15:0] coef5,
  13.     output reg [15:0] coef6,
  14.     output reg [15:0] coef7,
  15.     output reg [15:0] coef8,
  16.     output reg [15:0] coef9
  17.     );
  18.  
  19.     reg signed [15:0] mu;           //遗忘因子(步长)
  20.     reg        [3:0] cnt;           //计数器（计算一组滤波系数）
  21.     reg        [3:0] cnt_flag;      //计数器标志信号
  22.     reg              cnt_flag_en;   //计算使能信号
  23.  
  24. //延时寄存输入数据
  25.     reg signed [15:0] data_shift1;
  26.     reg signed [15:0] data_shift2;
  27.     reg signed [15:0] data_shift3;
  28.     reg signed [15:0] data_shift4;
  29.     reg signed [15:0] data_shift5;
  30.     reg signed [15:0] data_shift6;
  31.     reg signed [15:0] data_shift7;
  32.     reg signed [15:0] data_shift8;
  33.     reg signed [15:0] data_shift9;
  34.     
  35.     always @(posedge clk_i or negedge rst_n_i) begin
  36.         if(rst_n_i == 1'b0)begin
  37.             data_shift1 <= 16'd0;
  38.             data_shift2 <= 16'd0;
  39.             data_shift3 <= 16'd0;
  40.             data_shift4 <= 16'd0;
  41.             data_shift5 <= 16'd0;
  42.             data_shift6 <= 16'd0;
  43.             data_shift7 <= 16'd0;
  44.             data_shift8 <= 16'd0;
  45.             data_shift9 <= 16'd0;
  46.             mu          <= 16'd3;             //步长不知道是多少，随便写了一个;
  47.         end
  48.         else begin
  49.             data_shift1 <= data_in   ;
  50.             data_shift2 <= data_shift1;
  51.             data_shift3 <= data_shift2;
  52.             data_shift4 <= data_shift3;
  53.             data_shift5 <= data_shift4;
  54.             data_shift6 <= data_shift5;
  55.             data_shift7 <= data_shift6;
  56.             data_shift8 <= data_shift7;
  57.             data_shift9 <= data_shift8;
  58.         end
  59.     end       
  60. //权值更新
  62.     //mu*error*data_in*2
  63.     reg signed [15:0] coef1_reg;
  64.     reg signed [15:0] coef2_reg;
  65.     reg signed [15:0] coef3_reg;
  66.     reg signed [15:0] coef4_reg;
  67.     reg signed [15:0] coef5_reg;
  68.     reg signed [15:0] coef6_reg;
  69.     reg signed [15:0] coef7_reg;
  70.     reg signed [15:0] coef8_reg;
  71.     reg signed [15:0] coef9_reg;
  72.     
  73.  always @(posedge clk_i or negedge rst_n_i)
  74.     if(rst_n_i == 1'b0)
  75.         cnt <= 4'b0;
  76.     else if(cnt == 4'd13)
  77.         cnt <= 4'b0;
  78.     else
  79.         cnt <= cnt + 1'b1;
  80.         
  81.  always @(posedge clk_i or negedge rst_n_i)
  82.     if(rst_n_i == 1'b0)
  83.         cnt_flag <= 1'b0;
  84.     else if(cnt == 4'd13) 
  85.         cnt_flag <= 1'b1;
  86.     else
  87.         cnt_flag <= 1'b0;    
  88.         
  89.   always @(posedge clk_i or negedge rst_n_i)
  90.     if(rst_n_i == 1'b0)
  91.         cnt_flag_en <= 1'b0; 
  92.     else if(cnt_flag == 1'b1)
  93.         cnt_flag_en <= 1'b1;
  94.     else
  95.         cnt_flag_en <= cnt_flag_en;     
  96.      
  97. always@(posedge clk_i or negedge rst_n_i) 
  98. begin
  99.     if(rst_n_i == 1'b0)
  100.     begin
  101.         coef1_reg <= 16'd0;//2
  102.         coef2_reg <= 16'd0;
  103.         coef3_reg <= 16'd0;
  104.         coef4_reg <= 16'd0;
  105.         coef5_reg <= 16'd0;
  106.         coef6_reg <= 16'd0;
  107.         coef7_reg <= 16'd0;
  108.         coef8_reg <= 16'd0;
  109.         coef9_reg <= 16'd0;
  110.     end
  111.     else begin       
  112.         coef1_reg <= (mu * error_o * data_shift1);
  113.         coef2_reg <= (mu * error_o * data_shift2);
  114.         coef3_reg <= (mu * error_o * data_shift3);
  115.         coef4_reg <= (mu * error_o * data_shift4);
  116.         coef5_reg <= (mu * error_o * data_shift5);
  117.         coef6_reg <= (mu * error_o * data_shift6);
  118.         coef7_reg <= (mu * error_o * data_shift7);
  119.         coef8_reg <= (mu * error_o * data_shift8);
  120.         coef9_reg <= (mu * error_o * data_shift9);
  121.     end
  122. end
  124. always @(posedge clk_i or negedge rst_n_i) 
  125.     if(rst_n_i == 1'b0)
  126.     begin
  127.         coef1 <= 16'd0;//0
  128.         coef2 <= 16'd0;
  129.         coef3 <= 16'd0;
  130.         coef4 <= 16'd0;
  131.         coef5 <= 16'd0;
  132.         coef6 <= 16'd0;
  133.         coef7 <= 16'd0;
  134.         coef8 <= 16'd0;
  135.         coef9 <= 16'd0;  
  136.      end
  137.      else if(cnt_flag_en == 1'b1)
  138.      begin
  139.         coef1 <= coef1 + coef1_reg;
  140.         coef2 <= coef2 + coef2_reg;
  141.         coef3 <= coef3 + coef3_reg;
  142.         coef4 <= coef4 + coef4_reg;
  143.         coef5 <= coef5 + coef5_reg;
  144.         coef6 <= coef6 + coef6_reg;
  145.         coef7 <= coef7 + coef7_reg;
  146.         coef8 <= coef8 + coef8_reg;
  147.         coef9 <= coef9 + coef9_reg;
  148.       end
  149.  
  150. endmodule
  151.

testbench:

  1. module tb_lms(
  2. );
  3. reg clk_i;
  4. reg rst_n_i;
  5. reg [15:0] data_in;
  6. reg [15:0] data_ref;
  7. wire [15:0] error_o;
  8. wire [31:0] data_o;
  9. reg [15:0] mem1[1:4096];   //设计一个rom放读入的数据      
  10. reg [15:0] mem2[1:4096];                                 
  11. reg [12:0] i;
  12.  
  13.  //例化FIR滤波器
  14. lms_top lms_top_inst(
  15.     .clk_i(clk_i),
  16.     .rst_n_i(rst_n_i),
  17.     .data_in(data_in),        //输入待滤波数据
  18.     .data_ref(data_ref),       //参考数据
  19.     .error_o(error_o),         //误差
  20.     .data_o(data_o)         //输出数据
  21.     );
  22. initial                                               
  23.        begin 
  24.                      $readmemh("C:/Users/Lenovo/Desktop/LMS/matlab/add_noise_data.txt",mem1);//将待滤波信号读入mem
  25.                      $readmemh("C:/Users/Lenovo/Desktop/LMS/matlab/sin_data.txt",mem2);                   
  26.                      rst_n_i= 0;
  27.                      clk_i= 0;
  28.                      #50;rst_n_i= 1;
  29.                      #50000;
  30.                      $stop;
  31.        end  
  32.        
  33. initial
  34.        forever
  35.           #50 clk_i = ~clk_i;//时钟生成
  36.  
  37. always@(posedge clk_i or negedge rst_n_i) 
  38.       if(!rst_n_i)                                
  39.           data_in <= 16'b0 ;
  40.        else
  41.           data_in <= mem1[i];     //读入数据
  42.           
  43. always@(posedge clk_i or negedge rst_n_i) 
  44.       if(!rst_n_i)                                
  45.           data_ref <= 16'b0 ;
  46.        else
  47.           data_ref <= mem2[i];     //读入数据
  48.  
  49. always@(posedge clk_i or negedge rst_n_i) 
  50.       if(!rst_n_i)
  51.          i <= 12'd0;
  52.        else
  53.          i <= i + 1'd1;
  54. endmodule

整体RTL视图：

仿真：

 在这里我们可以看到data_in信号经过滤波器后，输出的data_o和期望信号data_ref的波形（已近很接近了），为什么输出不是一个完美的正弦波，其原因如下：1.步长因子。（在FPGA实现中我都步长因子设定为常数3）2.仿真时间（由于fpga的仿真时间一般都是以ns为单位的，滤波器的系数还没有迭代出一个完美系数）

（以上就是全部了，希望大佬们的指正。）

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