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Verilog设计倒计时秒表_verilog设计一个24秒倒计时器

作者：在线问答5 | 2024-07-07 19:20:30

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verilog设计一个24秒倒计时器

目录

一.设计要求

二.模块总和

三.模块设计

     1.顶层模块

     2.分频模块

     3.计数模块

     4.倒计时模块

     5.数码显示模块

     6.管脚约束代码

四.引脚分配

五.演示视频

一、设计要求

①.用基于NEXY4 DDR开发板自带的时钟驱动电路，要求计时精确；

②.用开发板上的低 7 个开关（sw6-sw0），输入倒计时的初始秒数（最大 99）；

③.用 2 个数码管以十进制显示当前的倒计时秒值；

④.用最高的开关（若开发板开关不够，可以用按键代替）实现 reset 功能；reset 后，能以 新的开关值进行倒计时。

⑤.当倒计时到 0 秒后，返回初始值继续倒计时。

二、模块总和

 三、模块设计

1.顶层模块

  1. module top(
  2. 	input clk,
  3. 	input rst_n,
  4. 	input [6:0]sw,
  5. 	output [7:0]sel,
  6. 	output [7:0]seg 
  7.     );
  8. wire clk_1s;
  9. wire [6:0]cnt;
  10. wire [3:0]en1;
  11. wire [3:0]en2;
  12.  
  13.  div div(
  14. 	.clk(clk),
  15. 	.rst_n(rst_n),
  16. 	.clk_1s(clk_1s)
  17.     );
  18. 	
  19.  count count(
  20. 	.clk(clk_1s),
  21. 	.rst_n(rst_n),
  22. 	.sw(sw),
  23. 	.cnt(cnt) 
  24.     );
  25. 	
  26.  countdown countdown(
  27. 	.clk(clk),
  28. 	.rst_n(rst_n),
  29. 	.cnt(cnt),
  30. 	.en1(en1),
  31. 	.en2(en2)
  32.     );
  33.  
  34.  digital digital(
  35. 	.clk(clk),
  36. 	.rst_n(rst_n),
  37. 	.en1(en1),
  38. 	.en2(en2),
  39. 	.seg(seg),
  40. 	.sel(sel)
  41.     );
  42. endmodule

2.分频模块

  1. module div(
  2. 	input clk,
  3. 	input rst_n,
  4. 	output reg clk_1s
  5.     );
  6.  
  7. reg [29:0]counter1;//计数器技术满0.5ms需要30位宽的计数器
  8. always @(posedge clk or negedge rst_n)
  9. 	if(!rst_n)
  10. 		counter1 <= 0;
  11. 	else if(counter1 == 49999999)
  12. 		counter1 <= 0;
  13. 	else 
  14. 		counter1 <= counter1 + 1;
  15.  
  16. always @(posedge clk or negedge rst_n)
  17. 	if(!rst_n)
  18. 		clk_1s <= 0;
  19. 	else if(counter1 == 49999999)
  20. 		clk_1s <= ~clk_1s;
  21. 	else 
  22. 		clk_1s <= clk_1s;
  23.  
  24. endmodule

 3.计数模块

  1. module count(
  2. 	input clk,
  3. 	input rst_n,
  4. 	input [6:0]sw,
  5. 	output reg [6:0]cnt //倒计时最大值99s
  6.     );
  7. 	
  8. always @(negedge clk or negedge rst_n)
  9. 	if(!rst_n)
  10. 		begin
  11. 			if(sw == 7'b000_0001)
  12. 				cnt <= 7'd1;
  13. 			else if(sw == 7'b000_0010)
  14. 				cnt <= 7'd5;
  15. 			else if(sw == 7'b000_0100)
  16. 				cnt <= 7'd10;
  17. 			else if(sw == 7'b000_1000)
  18. 				cnt <= 7'd20;
  19. 			else if(sw == 7'b001_0000)
  20. 				cnt <= 7'd25;
  21. 			else if(sw == 7'b010_0000)
  22. 				cnt <= 7'd30;
  23. 			else if(sw == 7'b100_0000)
  24. 				cnt <= 7'd35;
  25. 			else 
  26. 				cnt <= 0;
  27. 		end
  28. 	else if(cnt == 7'd99)
  29. 		cnt <= 0;
  30. 	else 
  31. 		cnt <= cnt + 1;
  32. endmodule

4.倒计时模块

  1. module countdown(
  2. 	input clk,
  3. 	input rst_n,
  4. 	input [6:0]cnt,
  5. 	output reg [3:0]en1,//个位
  6. 	output reg [3:0]en2//十位
  7.     );
  8.  
  9. always @(posedge clk or negedge rst_n)
  10. 	if(!rst_n)
  11. 		begin 
  12. 			en1 <= 0;
  13. 			en2 <= 0;
  14. 		end 
  15. 	else if(cnt <= 7'd99)
  16. 		begin 
  17. 			en1 <= (99-cnt)%10;
  18. 			en2 <= ((99-cnt)-en1)/10;
  19. 		end
  21. endmodule

5.数码显示模块

  1. module digital(
  2. 	input clk,
  3. 	input rst_n,
  4. 	input [3:0]en1,
  5. 	input [3:0]en2,
  6. 	output reg [7:0]seg,
  7. 	output reg [7:0]sel
  8.     );
  9. //计数1ms
  10. reg [16:0]counter2;//计数1ms 1000000/10= 100000
  11. always @(posedge clk or negedge rst_n)
  12. 	if(!rst_n)
  13. 		counter2 <= 0;
  14. 	else if(counter2 == 99999)
  15. 		counter2 <= 0;
  16. 	else
  17. 		counter2 <= counter2 + 1;
  18. //1ms时钟使能
  19. reg clk_1ms_en;
  20. always @(posedge clk or negedge rst_n)
  21. 	if(!rst_n)
  22. 		clk_1ms_en <= 0;
  23. 	else if(counter2 == 99999)
  24. 		clk_1ms_en <= 1;
  25. 	else 
  26. 		clk_1ms_en <= 0;
  27. //8位数码管计数器
  28. reg [2:0]counter3;
  29. always @(posedge clk or negedge rst_n)
  30. 	if(!rst_n)
  31. 		counter3 <= 0;
  32. 	else if(clk_1ms_en)
  33. 		counter3 <= counter3 + 1;
  34. 	else 	
  35. 		counter3 <= counter3;
  36. //8位数码管选择
  37. always @(posedge clk)
  38. 		case(counter3)
  39. 			0:sel <= 8'b1111_1110;
  40. 			1:sel <= 8'b1111_1101;
  41. 			2:sel <= 8'b1111_1111;
  42. 			3:sel <= 8'b1111_1111;
  43. 			4:sel <= 8'b1111_1111;
  44. 			5:sel <= 8'b1111_1111;
  45. 			6:sel <= 8'b1111_1111;
  46. 			7:sel <= 8'b1111_1111;
  47. 		endcase
  48. 	
  49. wire[31:0]data;
  50. assign data[3:0] = en1;
  51. assign data[7:4] = en2;
  52.  
  53. reg [3:0]dsp_data;
  54. always @(posedge clk)
  55. 		case(counter3)
  56. 			0:dsp_data <= data[3:0];
  57. 			1:dsp_data <= data[7:4];
  58. 			2:dsp_data <= data[11:8];
  59. 			3:dsp_data <= data[15:12];
  60. 			4:dsp_data <= data[19:16];
  61. 			5:dsp_data <= data[23:20];
  62. 			6:dsp_data <= data[27:24];
  63. 			7:dsp_data <= data[31:28];
  64. 		endcase
  65.  
  66. always @(posedge clk)
  67. 		case(dsp_data)
  68. 			4'd0:seg <= 8'b1100_0000;
  69. 			4'd1:seg <= 8'b1111_1001;
  70. 			4'd2:seg <= 8'b1010_0100;
  71. 			4'd3:seg <= 8'b1011_0000;
  72. 			4'd4:seg <= 8'b1001_1001;
  73. 			4'd5:seg <= 8'b1001_0010;
  74. 	        4'd6:seg <= 8'b1000_0010;
  75. 			4'd7:seg <= 8'b1111_1000;
  76. 			4'd8:seg <= 8'b1000_0000;
  77. 			4'd9:seg <= 8'b1001_0000;
  78. 		endcase 
  79. 	
  80. endmodule

6.管脚约束代码

  1. set_property IOSTANDARD LVCMOS33 [get_ports {seg[7]}]
  2. set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
  3. set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
  4. set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
  5. set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
  6. set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
  7. set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
  8. set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
  9. set_property IOSTANDARD LVCMOS33 [get_ports {sel[7]}]
  10. set_property IOSTANDARD LVCMOS33 [get_ports {sel[6]}]
  11. set_property IOSTANDARD LVCMOS33 [get_ports {sel[5]}]
  12. set_property IOSTANDARD LVCMOS33 [get_ports {sel[4]}]
  13. set_property IOSTANDARD LVCMOS33 [get_ports {sel[3]}]
  14. set_property IOSTANDARD LVCMOS33 [get_ports {sel[2]}]
  15. set_property IOSTANDARD LVCMOS33 [get_ports {sel[1]}]
  16. set_property IOSTANDARD LVCMOS33 [get_ports {sel[0]}]
  17. set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
  18. set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
  19. set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
  20. set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
  21. set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
  22. set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
  23. set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
  24. set_property IOSTANDARD LVCMOS33 [get_ports clk]
  25. set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
  26. set_property PACKAGE_PIN C12 [get_ports rst_n]
  27. set_property PACKAGE_PIN E3 [get_ports clk]
  28. set_property PACKAGE_PIN J15 [get_ports {sw[0]}]
  29. set_property PACKAGE_PIN L16 [get_ports {sw[1]}]
  30. set_property PACKAGE_PIN M13 [get_ports {sw[2]}]
  31. set_property PACKAGE_PIN R15 [get_ports {sw[3]}]
  32. set_property PACKAGE_PIN R17 [get_ports {sw[4]}]
  33. set_property PACKAGE_PIN T18 [get_ports {sw[5]}]
  34. set_property PACKAGE_PIN U18 [get_ports {sw[6]}]
  35. set_property PACKAGE_PIN U13 [get_ports {sel[7]}]
  36. set_property PACKAGE_PIN K2 [get_ports {sel[6]}]
  37. set_property PACKAGE_PIN T14 [get_ports {sel[5]}]
  38. set_property PACKAGE_PIN P14 [get_ports {sel[4]}]
  39. set_property PACKAGE_PIN J14 [get_ports {sel[3]}]
  40. set_property PACKAGE_PIN T9 [get_ports {sel[2]}]
  41. set_property PACKAGE_PIN J18 [get_ports {sel[1]}]
  42. set_property PACKAGE_PIN J17 [get_ports {sel[0]}]
  43. set_property PACKAGE_PIN H15 [get_ports {seg[7]}]
  44. set_property PACKAGE_PIN L18 [get_ports {seg[6]}]
  45. set_property PACKAGE_PIN T11 [get_ports {seg[5]}]
  46. set_property PACKAGE_PIN P15 [get_ports {seg[4]}]
  47. set_property PACKAGE_PIN K13 [get_ports {seg[3]}]
  48. set_property PACKAGE_PIN K16 [get_ports {seg[2]}]
  49. set_property PACKAGE_PIN R10 [get_ports {seg[1]}]
  50. set_property PACKAGE_PIN T10 [get_ports {seg[0]}]

四、引脚分配

 五、演示视频

IMG_2222

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